公开(公告)号：US09837505B2

公开(公告)日：2017-12-05

申请号：US14939311

申请日：2015-11-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/51 ,  H01L29/66 ,  H01L21/265 ,  H01L21/28 ,  H01L29/78 ,  H01L21/3115

CPC classification number: H01L29/512 ,  H01L21/265 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/31155 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: In a method for manufacturing a semiconductor device, a substrate is provided. A dummy gate is formed on the substrate. A first dielectric layer is formed to peripherally enclose the dummy gate over the substrate. A second dielectric layer is formed to peripherally enclose the first dielectric layer over the substrate. The second dielectric layer and the first dielectric layer are formed from different materials. An implant operation is performed on the first dielectric layer to form a first doped portion in the first dielectric layer. The dummy gate is removed to form a hole in the first dielectric layer. An operation of removing the dummy gate includes removing a portion of the first doped portion to form the hole having a bottom radial opening area and a top radial opening area which is greater than the bottom radial opening area. A metal gate is formed in the hole.

公开(公告)号：US09780092B2

公开(公告)日：2017-10-03

申请号：US15135476

申请日：2016-04-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/092 ,  H01L29/51 ,  H01L29/06 ,  H01L29/66 ,  H01L29/49 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: A semiconductor device includes a semiconductor substrate and at least one gate stack. The gate stack is present on the semiconductor substrate, and the gate stack includes at least one work function conductor and a filling conductor. The work function conductor has a recess therein. The filling conductor includes a plug portion and a cap portion. The plug portion is present in the recess of the work function conductor. The cap portion caps the work function conductor.

公开(公告)号：US09761483B1

公开(公告)日：2017-09-12

申请号：US15062226

申请日：2016-03-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/76 ,  H01L21/768 ,  H01L29/78 ,  H01L29/423 ,  H01L21/02

CPC classification number: H01L21/76834 ,  H01L21/02123 ,  H01L21/76802 ,  H01L29/42372 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Semiconductor devices, FinFET devices and methods of forming the same are disclosed. In accordance with some embodiments, a semiconductor device includes a substrate, a first gate stack, a first dielectric layer, a shielding layer and a connector. The first gate stack is over a substrate. The first dielectric layer is aside the first gate stack, wherein the top surface of the first gate stack is lower than the top surface of the first dielectric layer such that a first recess is provided above the first gate stack. The shielding layer is on the surface of the first recess and extends onto the top surface of the first dielectric layer. The connector is through the shielding layer and is electrically connected to the first gate stack.

公开(公告)号：US09748394B2

公开(公告)日：2017-08-29

申请号：US14813799

申请日：2015-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L29/423 ,  H01L21/3213

CPC classification number: H01L29/7856 ,  H01L21/32133 ,  H01L21/32137 ,  H01L29/42376 ,  H01L29/4916 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure. The gate stack includes a first portion and a second portion adjacent to the fin structure, and the first portion is wider than the second portion.

公开(公告)号：US20170229390A1

公开(公告)日：2017-08-10

申请号：US15071213

申请日：2016-03-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L23/528 ,  H01L21/02 ,  H01L21/768 ,  H01L23/532 ,  H01L29/06

CPC classification number: H01L23/528 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76883 ,  H01L23/53295 ,  H01L29/0649 ,  H01L2221/1031

Abstract: An interconnection and a method for manufacturing thereof are provided. The interconnection includes a first conductive layer, a dielectric layer, a second conductive layer, an insulation layer, and a plurality of air gaps. The first conductive layer is disposed over a semiconductor substrate. The dielectric layer is disposed over the first conductive layer. The second conductive layer penetrates through the dielectric layer to electrically connect with the first conductive layer. The insulation layer is located between a portion of the dielectric layer and the second conductive layer, and a material of the insulation layer and a material of the dielectric layer are different. The air gaps are located between another portion of the dielectric layer and the second conductive layer.

公开(公告)号：US09659813B1

公开(公告)日：2017-05-23

申请号：US15072277

申请日：2016-03-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L21/76831 ,  H01L21/76808 ,  H01L2221/1031

Abstract: An interconnection includes first and second conductive layers, first and second dielectric layers, a stop layer, and first and second adhesion layers is provided. The first conductive layer is disposed over a semiconductor substrate. The first dielectric layer is over the first conductive layer, and the first dielectric layer includes a via hole. The second dielectric layer is disposed over the first dielectric layer. The stop layer is located between the first dielectric layer and the second dielectric layer, and the second dielectric layer and the stop layer include a trench. The second conductive layer is located in the via hole and the trench to electrically connect with the first conductive layer. The first adhesion layer is located on sidewalls of the trench. The second adhesion layer is located between the second conductive layer and the first adhesion layer and between the second conductive layer and the first dielectric layer.

公开(公告)号：US09653364B1

公开(公告)日：2017-05-16

申请号：US14990796

申请日：2016-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L21/8238 ,  H01L23/535 ,  H01L27/092 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/823871 ,  H01L21/823814 ,  H01L21/823821 ,  H01L23/535 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

Abstract: Provided is a FinFET device including a substrate having at least one fin, first and second gate stacks, first and second strained layers, first and second dielectric layers, and first and second connectors. The first and second gate stacks are across the fin. The first and second strained layers are respectively aside the first and second gate stacks. The first and second dielectric layer are respectively over the first and second strained layers, and the top surface of the first dielectric layer is lower than the top surface of the second dielectric layer. The first connector is through the first dielectric layer and is electrically connected to the first strained layer. The second connector is through the second dielectric layer and is electrically connected to the second strained layer. Besides, the width of the second connector is greater than the width of the first connector.

公开(公告)号：US09536826B1

公开(公告)日：2017-01-03

申请号：US14799258

申请日：2015-07-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L23/52 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L29/78

CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76865 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L29/785

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first metal layer formed over a substrate and an interconnect structure formed over the first metal layer. The interconnect structure includes an upper portion, a middle portion and a lower portion, the middle portion is connected between the upper portion and the lower portion. The upper portion and the lower portion each have a constant width, and the middle portion has a tapered width which is gradually tapered from the upper portion to the lower portion.

Abstract translation: 提供半导体器件结构。 半导体器件结构包括形成在衬底上的第一金属层和形成在第一金属层上的互连结构。 互连结构包括上部，中部和下部，中间部分连接在上部和下部之间。 上部和下部各自具有恒定的宽度，并且中间部分具有从上部到下部逐渐变细的锥形宽度。

公开(公告)号：US09530887B1

公开(公告)日：2016-12-27

申请号：US15054046

申请日：2016-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L31/0312 ,  H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/02 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L29/7848 ,  H01L21/76831 ,  H01L21/76897 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851

Abstract: A fin-type field effect transistor device including a substrate, a gate stack structure, spacers and source and drain regions is described. The spacers includes first and second spacers and a first height of the first spacer is larger than a second height of the second spacer. A dielectric layer disposed on the gate stack structure includes a contact opening exposing the source and drain regions, the first and second spacers and a portion of the gate stack structure. A sheath structure is disposed within the contact opening and the sheath structure is in contact with the first and second spacers and the exposed portion of the gate stack structure without covering the source and drain regions. A metal connector is disposed within the sheath structure and connected to the source and drain regions.

Abstract translation: 描述了包括衬底，栅极堆叠结构，间隔物和源极和漏极区的鳍式场效应晶体管器件。 间隔件包括第一和第二间隔件，并且第一间隔件的第一高度大于第二间隔件的第二高度。 设置在栅极堆叠结构上的电介质层包括暴露源极和漏极区域的接触开口，第一和第二间隔物以及栅极堆叠结构的一部分。 护套结构设置在接触开口内，并且护套结构与第一和第二间隔件以及栅极堆叠结构的暴露部分接触而不覆盖源极和漏极区域。 金属连接器设置在护套结构内并连接到源区和漏区。

公开(公告)号：US09496363B1

公开(公告)日：2016-11-15

申请号：US14883445

申请日：2015-10-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/02 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/02271 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/515 ,  H01L29/66545 ,  H01L29/7851

Abstract: A semiconductor device includes a semiconductor device and a semiconductor fin on the semiconductor substrate, in which the semiconductor fin has a fin isolation structure at a common boundary that is shared by the two cells. The fin isolation structure has an air gap extending from a top of the semiconductor fin to a portion of the semiconductor substrate. The air gap divides the semiconductor fin into two portions of the semiconductor fin. The fin isolation structure includes a dielectric cap layer capping a top of the air gap.

Abstract translation: 半导体器件包括在半导体衬底上的半导体器件和半导体鳍片，其中半导体鳍片具有在由两个单元共享的公共边界处的鳍片隔离结构。 翅片隔离结构具有从半导体鳍片的顶部延伸到半导体衬底的一部分的气隙。 气隙将半导体翅片分成半导体翅片的两个部分。 翅片隔离结构包括覆盖气隙顶部的电介质盖层。