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    System and Method for a Pulse Generator
    363.
    发明申请
    System and Method for a Pulse Generator 有权
    脉冲发生器的系统和方法

    公开(公告)号：US20150365080A1

    公开(公告)日：2015-12-17

    申请号：US14304357

    申请日：2014-06-13

    Applicant: STMicroelectronics International N.V.

    Inventor： Shishir Kumar ,  Tanmoy Roy

    IPC: H03K5/01 ,  G11C8/18

    CPC classification number: H03K5/01 ,  G11C7/222 ,  G11C8/18

    Abstract: According to an embodiment, a method of generating a clock pulse includes receiving a leading edge at a clock input at a time when an enable signal is active, generating an edge at a clock output based on the received leading edge at the clock input, latching a logic value corresponding to the edge at the clock output, preventing changes at the clock input from affecting the latched logic value after the logic value is latched, resetting the latched logic value after a first delay time, and maintaining the reset logic value until a second edge is received at the clock input. The second edge at the clock input matches the leading edge at the clock input.

    Abstract translation: 根据实施例，一种产生时钟脉冲的方法包括在使能信号有效时在时钟输入端处接收前沿，在时钟输出端基于接收到的前沿产生时钟输出的边沿，锁存 对应于时钟输出端的逻辑值，防止在逻辑值被锁存之后时钟输入的变化影响锁存的逻辑值，在第一延迟时间之后复位锁存的逻辑值，并保持复位逻辑值直到 在时钟输入端接收第二个边沿。 时钟输入端的第二个边沿与时钟输入端的前沿匹配。

    Repair control logic for safe memories having redundant elements
    364.
    发明授权
    Repair control logic for safe memories having redundant elements 有权
    修复具有冗余元件的安全存储器的控制逻辑

    公开(公告)号：US09208040B2

    公开(公告)日：2015-12-08

    申请号：US14266067

    申请日：2014-04-30

    Applicant: STMicroelectronics International N.V.

    Inventor： Harsh Rawat ,  Kedar Janardan Dhori ,  Vinay Kumar ,  PraveenKumar Verma

    IPC: G06F11/00 ,  G06F11/20

    CPC classification number: G11C29/702 ,  G06F11/2094 ,  G06F2201/85

    Abstract: Repair control logic for a safe memory having redundant elements is provided. The repair control logic includes comparison logic including, for each bit slice of a memory array, a comparator circuit configured to determine whether a location value of an associated bit slice of the memory array is greater than a location value of a defective bit slice of the memory array, and data switching logic including, for each bit slice of the memory array, a switching circuit, responsive to a determination that the location value of the associated bit slice is greater than the location value of the defective bit slice, to switch data from the associated bit slice to an adjacent bit slice of the memory array.

    Abstract translation: 提供了具有冗余元件的安全存储器的修复控制逻辑。 修复控制逻辑包括比较逻辑，包括对于存储器阵列的每个位片，比较器电路被配置为确定存储器阵列的关联位片的位置值是否大于存储器阵列的有缺陷位片的位置值 存储器阵列和数据切换逻辑，包括对于存储器阵列的每个位片，响应于相关联的位片的位置值大于缺陷比特片的位置值的确定来切换数据，切换电路 从相关联的位片到存储器阵列的相邻位片。

    STAND-ALONE DC POWER SYSTEM FOR NETWORKS NOT CONNECTED TO THE GRID
    365.
    发明申请
    STAND-ALONE DC POWER SYSTEM FOR NETWORKS NOT CONNECTED TO THE GRID 有权
    用于网络的独立直流电源系统未连接到网络

    公开(公告)号：US20150323945A1

    公开(公告)日：2015-11-12

    申请号：US14275573

    申请日：2014-05-12

    Applicant: STMicroelectronics International N.V.

    Inventor： Laurent Perier

    IPC: G05F1/46

    CPC classification number: G05F1/46 ,  H02J1/00 ,  Y10T307/406

    Abstract: A stand-alone DC power network is provided with a DC to DC power converter only, and does not have a converter that will convert AC to DC. In addition, each of the different terminals that provides the DC voltage at different levels will be ranked according to priority as to which ones are the most important to supply the full voltage to, and which ones are of secondary importance in the event there is insufficient power in the system to provide full voltage at the specified current for the different loads. A processor monitors the voltage and current at each of the terminals, and in the event a current is attempted to be drawn from the system which would cause a first priority terminal to be reduced in voltage, the processor will instead reduce the power provided to the second priority terminal and ensure that the first priority terminal does not have a significant reduction in the specified voltage or the amount of current supplied to that terminal at the specified voltage.

    Abstract translation: 一个独立的直流电源网络只提供一个直流到直流电源转换器，并没有一个可以将交流转换成直流电的转换器。 此外，提供不同电平的直流电压的不同终端中的每一个将根据优先级来排列，哪些是提供全电压最重要的哪一个，以及在不充分的情况下哪些最重要 系统中的电源为不同负载的指定电流提供全电压。 处理器监视每个终端处的电压和电流，并且在尝试从系统中抽出电流以使得第一优先级终端电压降低的情况下，处理器将代替地减少提供给 第二优先级终端，并确保第一优先级终端在指定电压下没有明显减小指定电压或提供给该终端的电流量。

    MONITORING ON-CHIP CLOCK CONTROL DURING INTEGRATED CIRCUIT TESTING
    366.
    发明申请
    MONITORING ON-CHIP CLOCK CONTROL DURING INTEGRATED CIRCUIT TESTING 有权
    在集成电路测试期间监控片上时钟控制

    公开(公告)号：US20150323594A1

    公开(公告)日：2015-11-12

    申请号：US14270964

    申请日：2014-05-06

    Applicant: STMicroelectronics International N.V.

    Inventor： Shray KHULLAR ,  Swapnil BAHL

    IPC: G01R31/3177

    CPC classification number: G01R31/31727 ,  G01R31/2815 ,  G01R31/31704 ,  G01R31/31705 ,  G01R31/3177 ,  G01R31/318552 ,  G01R31/318594

    Abstract: The On-Chip Clock (OCC) circuit is for testing an integrated circuit having logic blocks connected in scan chains. An OCC controller is configured to receive a plurality of clock signals and output a plurality of shift/capture clock signals for use by the scan chains of logic blocks, the plurality of shift/capture clock signals including at least two consecutive at-speed capture clock pulses. An OCC monitor is configured to provide a verification of OCC operation based upon the at least two consecutive at-speed capture clock pulses. The OCC monitor may include a plurality of registers configured to provide delayed pulses based upon the at least two consecutive at-speed capture clock pulses, a counter configured to count differences between the delayed pulses, and an output register coupled to the counter and configured to provide a static data verification (e.g. output on an integrated circuit pad) for the test engineer.

    Abstract translation: 片内时钟（OCC）电路用于测试具有连接在扫描链中的逻辑块的集成电路。 OCC控制器被配置为接收多个时钟信号并输出​​多个移位/捕获时钟信号以供逻辑块的扫描链使用，所述多个移位/捕获时钟信号包括至少两个连续的低速捕获时钟 脉冲。 OCC监视器被配置为基于至少两个连续的在线捕获时钟脉冲来提供对OCC操作的验证。 OCC监视器可以包括多个寄存器，其被配置为基于至少两个连续的在线捕获时钟脉冲提供延迟的脉冲，配置为对延迟的脉冲之间的差异进行计数的计数器，以及耦合到计数器的输出寄存器，并被配置为 为测试工程师提供静态数据验证（例如集成电路板上的输出）。

    REPAIR CONTROL LOGIC FOR SAFE MEMORIES HAVING REDUNDANT ELEMENTS
    367.
    发明申请
    REPAIR CONTROL LOGIC FOR SAFE MEMORIES HAVING REDUNDANT ELEMENTS 有权
    具有冗余元素的安全记录的维修控制逻辑

    公开(公告)号：US20150317225A1

    公开(公告)日：2015-11-05

    申请号：US14266067

    申请日：2014-04-30

    Applicant: STMicroelectronics International N.V.

    Inventor： Harsh Rawat ,  Kedar Janardan Dhori ,  Vinay Kumar ,  PraveenKumar Verma

    IPC: G06F11/20

    CPC classification number: G11C29/702 ,  G06F11/2094 ,  G06F2201/85

    Abstract: Repair control logic for a safe memory having redundant elements is provided. The repair control logic includes comparison logic including, for each bit slice of a memory array, a comparator circuit configured to determine whether a location value of an associated bit slice of the memory array is greater than a location value of a defective bit slice of the memory array, and data switching logic including, for each bit slice of the memory array, a switching circuit, responsive to a determination that the location value of the associated bit slice is greater than the location value of the defective bit slice, to switch data from the associated bit slice to an adjacent bit slice of the memory array.

    Abstract translation: 提供了具有冗余元件的安全存储器的修复控制逻辑。 修复控制逻辑包括比较逻辑，包括对于存储器阵列的每个位片，比较器电路被配置为确定存储器阵列的关联位片的位置值是否大于存储器阵列的有缺陷位片的位置值 存储器阵列和数据切换逻辑，包括对于存储器阵列的每个位片，响应于相关联的位片的位置值大于缺陷比特片的位置值的确定来切换数据，切换电路 从相关联的位片到存储器阵列的相邻位片。

    Wide voltage range high performance sense amplifier
    368.
    发明授权
    Wide voltage range high performance sense amplifier 有权
    宽电压范围高性能读出放大器

    公开(公告)号：US09177637B1

    公开(公告)日：2015-11-03

    申请号：US14472166

    申请日：2014-08-28

    Applicant: STMicroelectronics International N.V.

    Inventor： Anuj Grover ,  Gangaikondan Subramani Visweswaran

    IPC: G11C11/00 ,  G11C11/419 ,  G11C7/06

    CPC classification number: G11C11/419 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1048 ,  G11C2207/002

    Abstract: A dual rail SRAM array includes a plurality of columns of memory cells each coupled between two bit lines. A sense amplifier is coupled between each pair of bit lines. Capacitors are positioned between the sense amplifier outputs and the bit lines, thereby separating the sense amplifier from the bit lines. The memory cells are powered with an array supply voltage. The sense amplifier is powered with a peripheral supply voltage. During a read operation of the memory array, the bit lines are precharged to the array supply voltage. The sense amplifier is precharged to the peripheral supply voltage or to an intermediate voltage.

    Abstract translation: 双轨SRAM阵列包括多个存储单元列，每个存储单元分别耦合在两个位线之间。 读出放大器耦合在每对位线之间。 电容器位于感测放大器输出和位线之间，从而将读出放大器与位线分离。 存储单元由阵列电源电压供电。 读出放大器由周边电源供电。 在存储器阵列的读取操作期间，位线被预充电到阵列电源电压。 读出放大器被预充电到外围电源电压或中间电压。

    Integrated circuit board with wireless circuitry
    369.
    再颁专利
    Integrated circuit board with wireless circuitry 有权
    集成电路板与无线电路

    公开(公告)号：USRE45769E1

    公开(公告)日：2015-10-20

    申请号：US14222900

    申请日：2014-03-24

    Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

    Inventor： Francesco Varone ,  Amedeo Veneroso

    IPC: H04M1/00 ,  G06Q20/34 ,  G06F9/445

    CPC classification number: G06Q20/341 ,  G06F9/445

    Abstract: An IC Card comprises a first device, including a first processor and a first memory unit, to communicate with a handset, and a second device. The second device includes a second processor and a second memory unit, to communicate via a wireless communication with an electronic apparatus external to the handset, the second device providing predetermined services. Each predetermined service is programmed to receive a wireless message from a respective electronic apparatus, to execute a predetermined elaboration operation, and to return a result to the respective electronic apparatus. The second memory unit stores a plurality of additional programs for executing additional elaborations operations, each program being associated to one of the predetermined services. The second device has a run-time environment for executing the additional programs when the corresponding predetermined services receives the wireless message.

    Abstract translation: IC卡包括第一设备，包括第一处理器和第一存储器单元，以与手机通信，以及第二设备。 第二设备包括第二处理器和第二存储器单元，用于经由与手机外部的电子设备的无线通信进行通信，第二设备提供预定的服务。 每个预定服务被编程为从相应的电子设备接收无线消息，执行预定的详细操作，并将结果返回到各个电子设备。 第二存储器单元存储用于执行附加精细化操作的多个附加程序，每个程序与预定服务之一相关联。 当相应的预定服务接收到无线消息时，第二设备具有用于执行附加程序的运行时环境。

    Power measurement circuit
    370.
    发明授权
    Power measurement circuit 有权
    功率测量电路

    公开(公告)号：US09167023B2

    公开(公告)日：2015-10-20

    申请号：US14078118

    申请日：2013-11-12

    Applicant: STMicroelectronics International N.V.

    Inventor： Surinder Pal Singh ,  Kaushik Saha

    IPC: G01R19/18 ,  H04L29/08 ,  G01R21/133 ,  G01R19/22 ,  H04L12/24

    CPC classification number: H04L67/025 ,  G01R19/22 ,  G01R21/133 ,  H04L41/32

    Abstract: A system for power measurement in an electronic device includes a sensing unit, an analog-to-digital converter (ADC) and a controller. The sensing unit senses voltage across a power source and modulates a carrier signal based on the sensed voltage. The ADC converts a combination of the modulated carrier signal and audio signals received by the electronic device to generate a digitized combined signal and provides the digitized combined signal to the controller. The controller separates digitized modulated carrier signal and digitized audio signals. The digitized modulated carrier signal is demodulated to generate an output signal that provides a measure of the power consumed by the electronic device.

    Abstract translation: 电子设备中的功率测量系统包括感测单元，模数转换器（ADC）和控制器。 感测单元感测电源两端的电压，并根据检测到的电压调制载波信号。 ADC转换由电子设备接收的调制载波信号和音频信号的组合，以产生数字化的组合信号，并将数字化的组合信号提供给控制器。 控制器分离数字化调制载波信号和数字化音频信号。 数字化调制载波信号被解调以产生提供电子设备消耗的功率的量度的输出信号。

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