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    METHOD AND APPARATUS FOR A DRAM CACHE TAG PREFETCHER
    382.
    发明申请
    METHOD AND APPARATUS FOR A DRAM CACHE TAG PREFETCHER 有权

    公开(公告)号：US20220318151A1

    公开(公告)日：2022-10-06

    申请号：US17219782

    申请日：2021-03-31

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Jagadish B. Kotra ,  Marko Scrbak ,  Matthew Raymond Poremba

    IPC: G06F12/0891 ,  G06F12/0853 ,  G06F12/0862 ,  G06F3/06

    Abstract: Devices and methods for cache prefetching are provided. A device is provided which comprises memory and a processor. The memory comprises a DRAM cache, a cache dedicated to the processor and one or more intermediate caches between the dedicated cache and the DRAM cache. The processor is configured to issue prefetch requests to prefetch data, issue data access requests to fetch the data and when one or more previously issued prefetch requests are determined to be inaccurate, issue a prefetch request to prefetch a tag, corresponding to the memory address of requested data in the DRAM cache. A tag look-up is performed at the DRAM cache without performing tag look-ups at the dedicated cache or the intermediate caches. The tag is prefetched from the DRAM cache without prefetching the requested data.

    PROCESSING-IN-MEMORY CONCURRENT PROCESSING SYSTEM AND METHOD
    383.
    发明申请
    PROCESSING-IN-MEMORY CONCURRENT PROCESSING SYSTEM AND METHOD 有权

    公开(公告)号：US20220318012A1

    公开(公告)日：2022-10-06

    申请号：US17217792

    申请日：2021-03-30

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Muhammad Amber HASSAAN ,  Michael L. CHU ,  Ashwin AJI

    IPC: G06F9/30

    Abstract: A processing system includes a processing unit and a memory device. The memory device includes a processing-in-memory (PIM) module that performs processing operations on behalf of the processing unit. An instruction set architecture (ISA) of the PIM module has fewer instructions than an ISA of the processing unit. Instructions received from the processing unit are translated such that processing resources of the PIM module are virtualized. As a result, the PIM module concurrently performs processing operations for multiple threads or applications of the processing unit.

    APPROACH FOR ENFORCING ORDERING BETWEEN MEMORY-CENTRIC AND CORE-CENTRIC MEMORY OPERATIONS
    384.
    发明申请
    APPROACH FOR ENFORCING ORDERING BETWEEN MEMORY-CENTRIC AND CORE-CENTRIC MEMORY OPERATIONS 有权

    公开(公告)号：US20220317926A1

    公开(公告)日：2022-10-06

    申请号：US17219446

    申请日：2021-03-31

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Shaizeen Aga ,  Nuwan Jayasena ,  Johnathan Alsop

    IPC: G06F3/06

    Abstract: Ordering between memory-centric memory operations, referred to hereinafter as “MC-Mem-Ops,” and core-centric memory operations, referred to hereinafter as “CC-Mem-Ops,” is enforced using inter-centric fences, referred to hereinafter as an “IC-fences.” IC-fences are implemented by an ordering primitive or ordering instruction, that cause a memory controller, a cache controller, etc., to enforce ordering of MC-Mem-Ops and CC-Mem-Ops throughout the memory pipeline and at the memory controller by not reordering MC-Mem-Ops (or sometimes CC-Mem-Ops) that arrive before the IC-fence to after the IC-fence. Processing of an IC-fence also causes the memory controller to issue an ordering acknowledgment to the thread that issued the IC-fence instruction. IC-fences are tracked at the core and designated as complete when the ordering acknowledgment is received. Embodiments include a completion level-specific cache flush operation which, when used with an IC-fence, provides proper ordering between cached CC-Mem-Ops and MC-Mem-ops with reduced data transfer and completion times.

    DATA FABRIC CLOCK SWITCHING
    386.
    发明申请
    DATA FABRIC CLOCK SWITCHING 有权

    公开(公告)号：US20220317755A1

    公开(公告)日：2022-10-06

    申请号：US17219407

    申请日：2021-03-31

    Applicant: Advanced Micro Devices, Inc.

    Inventor： James R. Magro ,  Christopher Weaver ,  Abhishek Kumar Verma

    IPC: G06F1/3234 ,  G06F1/3225 ,  G06F1/3287 ,  G06F1/08 ,  G06F3/06

    Abstract: A memory controller couples to a data fabric clock domain, and to a physical layer interface circuit PHY clock domain. A first interface circuit adapts transfers between the data fabric clock domain (FCLK) and the memory controllers clock domain, and a second interface circuit couples the memory controller to the PHY clock domain. A power controller responds to a power state change request by sending commands to the second interface circuit to change parameters of a memory system and to update a set of timing parameters of the memory controller according to a selected power state of a plurality of power states. The power controller further responds to a request to synchronize with a new frequency on the FCLK domain by changing a set of timing parameters of the clock interface circuit without changing the set of timing parameters of the memory system or the selected power state.

    Distributed user mode processing
    387.
    发明授权
    Distributed user mode processing 有权

    公开(公告)号：US11461137B2

    公开(公告)日：2022-10-04

    申请号：US16721456

    申请日：2019-12-19

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Rex Eldon McCrary

    IPC: G06F9/54 ,  G06F9/48 ,  G06F9/38 ,  G06F12/0831 ,  G06F9/30

    Abstract: A first processing unit such as a graphics processing unit (GPU) pipelines that execute commands and a scheduler to schedule one or more first commands for execution by one or more of the pipelines. The one or more first commands are received from a user mode driver in a second processing unit such as a central processing unit (CPU). The scheduler schedules one or more second commands for execution in response to completing execution of the one or more first commands and without notifying the second processing unit. In some cases, the first processing unit includes a direct memory access (DMA) engine that writes blocks of information from the first processing unit to a memory. The one or more second commands program the DMA engine to write a block of information including results generated by executing the one or more first commands.

    SYNCHRONIZATION FREE CROSS PASS BINNING THROUGH SUBPASS INTERLEAVING
    388.
    发明申请
    SYNCHRONIZATION FREE CROSS PASS BINNING THROUGH SUBPASS INTERLEAVING 有权

    公开(公告)号：US20220309729A1

    公开(公告)日：2022-09-29

    申请号：US17565394

    申请日：2021-12-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Ruijin Wu ,  Mika Tuomi ,  Paavo Sampo Ilmari Pessi ,  Anirudh R. Acharya

    IPC: G06T15/00 ,  G06T1/20

    Abstract: A method of tiled rendering is provided which comprises dividing a frame to be rendered, into a plurality of tiles, receiving commands to execute a plurality of subpasses of the tiles and interleaving execution of same subpasses of multiple tiles of the frame. Interleaving execution of same subpasses of multiple tiles comprises executing a previously ordered first subpass of a second tile between execution of the previously ordered first subpass of a first tile and execution of a subsequently ordered second subpass of the first tile. The interleaving is performed, for example, by executing the plurality of subpasses in an order different from the order in which the commands to execute the plurality of subpasses are stored and issued. Alternatively, interleaving is performed by executing one or more subpasses as skip operations such that the plurality of subpasses are executed in the same order.

    DYNAMICALLY RECONFIGURABLE REGISTER FILE
    389.
    发明申请
    DYNAMICALLY RECONFIGURABLE REGISTER FILE 有权

    公开(公告)号：US20220309606A1

    公开(公告)日：2022-09-29

    申请号：US17214762

    申请日：2021-03-26

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Pramod Vasant Argade ,  Martin G. Sarov ,  Milind N. Nemlekar

    IPC: G06T1/20 ,  G06F9/30 ,  G06F9/52

    Abstract: Techniques for managing register allocation are provided. The techniques include detecting a first request to allocate first registers for a first wavefront; first determining, based on allocation information, that allocating the first registers to the first wavefront would result in a condition in which a deadlock is possible; in response to the first determining, refraining from allocating the first registers to the first wavefront; detecting a second request to allocate second registers for a second wavefront; second determining, based on the allocation information, that allocating the second registers to the second wavefront would result in a condition in which deadlock is not possible; and in response to the second determining, allocating the second registers to the second wavefront.

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