公开(公告)号：USRE36208E

公开(公告)日：1999-05-11

申请号：US230809

申请日：1994-04-21

申请人： Francis Steffen

发明人： Francis Steffen

IPC分类号： B65D85/57 ,  B29C65/08 ,  B42D15/10 ,  G06K19/077 ,  G09F1/10 ,  H01L21/50 ,  H05K5/00 ,  H05K1/14

CPC分类号： B29C66/54 ,  B29C65/08 ,  B29C66/12449 ,  B29C66/30223 ,  B29C66/9516 ,  G06K19/07743 ,  H01L21/50 ,  B29C66/73921 ,  B29L2017/00 ,  B29L2031/3425

摘要： A housing designed to contain a logic circuit (15) comprising two shells (11a, 11b) each including a welding area (17a, 17b) having an appropriate geometry permitting ultrasonic welding, such that when both shells are assembled before a welding phase, they are shifted along a vertical axis (20). The supporting plate (13) comprises a mounting ear (23) while the shells comprise a receptacle (33a, 33b). During the welding phase, there is no concomitant contact between any of the upper face (26) and lower face (27) of the ear (23) and the corresponding bearing faces (34a, 34b) of the receptacles, owing to a shift (21). The shift is reduced and the concomitant contact takes place between the bearing faces (34a, 34b) of the receptacles and each of the upper and lower faces (26, 27) of the ear (23) only when the welding phase is completed.

摘要翻译： 一种被设计成容纳包括两个壳体（11a，11b）的逻辑电路（15）的壳体，每个壳体包括具有允许超声波焊接的适当几何形状的焊接区域（17a，17b），使得当两个壳体在焊接阶段之前组装时， 沿着垂直轴线（20）移动。 支撑板（13）包括安装耳（23），而壳包括插座（33a，33b）。 在焊接阶段期间，由于偏移（图3），接触器的上表面（26）和下表面（27）和插座的相应的支承面（34a，34b）之间没有任何接触， 21）。 只有当焊接阶段完成时，移位减小，并且容纳器的支承面（34a，34b）和耳朵（23）的每个上表面和下表面（26,27）之间发生伴随的接触。

公开(公告)号：US5886555A

公开(公告)日：1999-03-23

申请号：US828159

申请日：1997-03-27

申请人： Marco Bildgen ,  Maxime Tessier

发明人： Marco Bildgen ,  Maxime Tessier

IPC分类号： H02P25/02 ,  H02P27/08 ,  H03K7/08

CPC分类号： H03K7/08 ,  H02P25/024

摘要： To produce pulses in a cyclically repetitive mode while modifying the production frequency, a counter looped on itself is used. The outputs of this counter are connected to the address inputs of a memory. The signals read in the memory represent pulses to be produced. When it is sought to increase the period of reading the totality of the memory gradually, some of the words of this memory are read for a greater period of time. In the invention, words are chosen for which this addressing will be maintained by comparing the reverse of the reading address with a given value and by deciding, as a function of the result of this comparison, whether the word read at this address must be read for a longer duration or not. It is shown that this circuit is very easy to make and requires but few components. The circuit made can be used particularly in the field of the control of three-phase synchronous motors.

摘要翻译： 为了在修改生产频率的同时以循环重复模式产生脉冲，使用自身循环的计数器。 该计数器的输出连接到存储器的地址输入。 在存储器中读取的信号表示要产生的脉冲。 当寻求逐渐增加读取记忆的周期时，这个记忆的一些字被读取更长的一段时间。 在本发明中，通过将读取地址的反向与给定值进行比较并且通过根据该比较的结果来确定在该地址读取的字是否必须被读取来选择将保持该寻址的字 持续时间较长或不长。 这表明这个电路很容易制造，只需要很少的组件。 所制造的电路可以特别用于三相同步电动机的控制领域。

公开(公告)号：US5886549A

公开(公告)日：1999-03-23

申请号：US792962

申请日：1997-01-24

申请人： David Naura

发明人： David Naura

IPC分类号： H03K17/22

CPC分类号： H03K17/223 ,  H03K17/22

摘要： The invention relates to a device to neutralize an electronic circuit when it is being powered or disconnected. It can be applied more particularly to electronic circuits powered by low voltages on the order of 1.8 volts. The device of the invention is not significantly affected by variations, due to manufacturing conditions, in the values of its components. The invention may be applied to the field of programmable electrical memories.

公开(公告)号：US5883831A

公开(公告)日：1999-03-16

申请号：US940193

申请日：1997-09-29

申请人： Joaquim Ramon Lopez ,  David Naura

发明人： Joaquim Ramon Lopez ,  David Naura

IPC分类号： G11C7/24 ,  G11C16/22 ,  G11C11/34

CPC分类号： G11C7/24 ,  G11C16/22

摘要： Disclosed is a serial access memory and a method of writing in said memory comprising at least one matrix of memory cells, a clock signal input terminal receiving a clock signal, a data input terminal receiving a defined number of data bits in series and a selection terminal receiving a selection signal, said method being initialized when the selection signal changes state from a first state to a second state. The writing in the matrix of memory cells occurs only if the selection signal goes from the second state to the first state during a window located just after the last of the data bits has been received.

摘要翻译： 公开了一种串行存取存储器和一种在所述存储器中写入的方法，所述存储器包括至少一个存储单元矩阵，接收时钟信号的时钟信号输入端，串行接收定义数量的数据位的数据输入端和选择端 接收选择信号，当所述选择信号将状态从第一状态改变到第二状态时，所述方法被初始化。 仅在接收到最后一个数据位之后的窗口期间，只有在选择信号从第2状态变为第1状态时，存储单元矩阵的写入才发生。

公开(公告)号：US5883500A

公开(公告)日：1999-03-16

申请号：US805823

申请日：1997-02-26

申请人： Robert Pezzani

发明人： Robert Pezzani

IPC分类号： H03K17/725 ,  G05F1/00

CPC分类号： H03K17/725 ,  H01L29/747

摘要： A three-state switch designed to be inserted in an ac supply circuit and associated with a state selection circuit. In a first state, the switch is open and does not allow current to flow. In a second state, the switch allows current of a first polarity to flow. In a third state, the switch allows a current of a second polarity to flow. The switch includes a cathode gate thyristor and an anode gate thyristor connected head-to-tail, the gate of the cathode gate thyristor forming a control terminal and being connected through a resistor to the gate of the anode gate thyristor.

摘要翻译： 三态开关设计成插入到交流电源电路中并与状态选择电路相关联。 在第一状态下，开关断开，不允许电流流动。 在第二状态下，开关允许第一极性的电流流动。 在第三状态下，开关允许第二极性的电流流动。 该开关包括一个阴极栅极晶闸管和一个前后连接的阳极栅极晶闸管，阴极栅极晶闸管的栅极形成一个控制端子，并通过电阻连接到阳极栅极晶闸管的栅极。

公开(公告)号：US5883401A

公开(公告)日：1999-03-16

申请号：US650127

申请日：1996-05-17

申请人： Robert Pezzani

发明人： Robert Pezzani

IPC分类号： H05B41/18 ,  H01L21/822 ,  H01L27/04 ,  H01L29/74 ,  H01L29/747 ,  H01L29/866 ,  H03K17/725 ,  H05B41/04 ,  H01L31/111

CPC分类号： H03K17/725 ,  H05B41/046 ,  Y10S315/05

摘要： A monolithic semiconductor component has a first thyristor having a gate, an anode and a cathode. The gate is connected to the cathode through a first resistor and to the anode through the series connection of a zener diode and a second thyristor. The thyristors are of the vertical type and the zener diode is of the lateral type. The cathode of the zener diode is connected to the cathode of the second thyristor through a metallization forming an output terminal.

摘要翻译： 单片半导体元件具有第一晶闸管，其具有栅极，阳极和阴极。 栅极通过第一电阻器连接到阴极，并通过齐纳二极管和第二晶闸管的串联连接到阳极。 晶闸管为垂直型，齐纳二极管为侧面型。 齐纳二极管的阴极通过形成输出端的金属化连接到第二晶闸管的阴极。

公开(公告)号：US5870593A

公开(公告)日：1999-02-09

申请号：US861357

申请日：1997-05-21

申请人： Jacques Prunier ,  Laurent Lusinchi

发明人： Jacques Prunier ,  Laurent Lusinchi

IPC分类号： H04B10/114 ,  H04L27/04 ,  G06F1/04

CPC分类号： H04B10/1141 ,  H04L27/04

摘要： The present invention relates to a method for generating pulse trains by means of a microprocessor, consisting of generating an envelope signal by means of a timer which is programmable by a CPU, the width of a square wave of the envelope signal corresponding to the width of the pulse trains, generating a carrier signal having a predetermined frequency, and modulating the envelope signal with the carrier.

摘要翻译： 本发明涉及一种通过微处理器生成脉冲串的方法，包括通过可由CPU编程的定时器产生包络信号，包络信号的方波宽度对应于 脉冲串，产生具有预定频率的载波信号，并用载波调制包络信号。

公开(公告)号：US5867374A

公开(公告)日：1999-02-02

申请号：US739705

申请日：1996-10-29

申请人： Jean-Michel Moreau

发明人： Jean-Michel Moreau

IPC分类号： H02M1/00 ,  H02M1/42 ,  H02M3/335 ,  H02M7/537

CPC分类号： H02M1/4258 ,  H02M3/335 ,  Y02B70/126 ,  Y02P80/112

摘要： A method and apparatus for providing a rectified voltage to a flyback switch-mode supply circuit with power factor correction is disclosed and claimed. The invention comprises a rectifying bridge and a charge path for charging a capacitor from the rectified voltage obtained from the output of the bridge. The degree of power factor correction is achieved by selecting a time at which either the rectifying bridge output or the capacitor provides a voltage to the supply circuit. The input to the supply circuit is a primary winding having n1 turns between an upper and intermediate tap, and n2 turns between an intermediate and lower tap. The capacitor is connected to the upper tap via a diode, a first rectifying bridge output is connected to the intermediate tap via a diode, and a second rectifying bridge output is connected to the lower tap via a controllable switch. When the rectified voltage is greater than a threshold voltage related to the peak rectified voltage by the ratio n2/(n1+n2), the rectifying bridge outputs provide the voltage to the supply circuit. When the rectified voltage is lower than this threshold voltage, the capacitor provides the voltage to the supply circuit. In this manner, the timing of sources providing voltage to the supply circuit and hence the degree of power factor correction is determined by the ratio of the primary winding turns n1 and n2.

摘要翻译： 公开并要求保护用于向具有功率因数校正的反激式开关模式电源电路提供整流电压的方法和装置。 本发明包括整流桥和充电路径，用于从从桥的输出获得的整流电压对电容器充电。 通过选择整流桥输出或电容器向电源电路提供电压的时间来实现功率因数校正的程度。 供给电路的输入是在上部和中间抽头之间具有n1匝的初级绕组，并且n2在中间和下部抽头之间转动。 电容器通过二极管连接到上部抽头，第一整流桥输出通过二极管连接到中间抽头，第二整流桥输出通过可控开关连接到下抽头。 当整流电压大于与峰值整流电压相关的阈值电压乘以n2 /（n1 + n2）时，整流桥输出向电源电路提供电压。 当整流电压低于该阈值电压时，电容器向电源电路提供电压。 以这种方式，通过初级绕组匝数n1和n2的比率确定向电源电路提供电压的源的定时以及功率因数校正的程度。

公开(公告)号：US5861773A

公开(公告)日：1999-01-19

申请号：US982979

申请日：1997-12-02

申请人： Jacques Meyer

发明人： Jacques Meyer

IPC分类号： H04L27/00 ,  H04L27/227 ,  H04L27/38 ,  H04L27/22

CPC分类号： H04L27/3827 ,  H04L27/2273 ,  H04L2027/0057 ,  Y10S331/02

摘要： A method for detecting a locked condition of a demodulator of at least one signal that may have discrete levels defining a constellation of nominal points in a plane. The method includes the steps of defining reference areas about the nominal points, a reference area being separated from another by a band or an angular sector crossing the origin of the constellation plane, and indicating a locked condition if the ratio of points occurring in the reference areas is above the probability for points to occur in the reference area, when the demodulator is wrongly adjusted.

摘要翻译： 一种用于检测至少一个信号的解调器的锁定状态的方法，该信号可以具有定义平面中的标称点的星座的离散电平。 该方法包括以下步骤：定义关于标称点的参考区域，参考区域与带状物或与星座图平面的原点相交的角扇区与另一参考区域分离，并且如果参考点中出现的点的比率指示锁定条件 当解调器错误调整时，区域高于参考区域中出现点的概率。

公开(公告)号：US5859526A

公开(公告)日：1999-01-12

申请号：US871096

申请日：1997-06-06

申请人： Tien-Dung Do ,  Mathieu Lisart

发明人： Tien-Dung Do ,  Mathieu Lisart

IPC分类号： G05F3/24 ,  G11C5/14 ,  G05F1/40

CPC分类号： G11C5/147 ,  G05F3/242

摘要： A voltage reference generator includes a voltage source and a differential amplifier. The voltage source supplies a stable voltage reference to a positive input of the differential amplifier which is configured as a follower having its output looped back to its negative input. The negative feedback loop is a variable-resistance loop that is controlled by the output of the differential amplifier. The variable-resistance feedback loop transiently imposes open-loop operation when the voltage reference generator is turned on so as to provide high current to the output before imposing closed-loop operation in follower mode.

摘要翻译： 电压基准发生器包括电压源和差分放大器。 电压源为差分放大器的正输入提供稳定的参考电压，差分放大器的正输入被配置为具有循环回到其负输入的引导器。 负反馈回路是由差分放大器的输出控制的可变电阻回路。 当电压基准发生器导通时，可变电阻反馈环路瞬时施加开环操作，以便在跟随器模式下施加闭环操作之前向输出端提供高电流。