公开(公告)号：US08582379B2

公开(公告)日：2013-11-12

申请号：US12917708

申请日：2010-11-02

Applicant: Hong-Chen Cheng ,  Chih-Chieh Chiu ,  Chung-Ji Lu ,  Cheng Hung Lee

Inventor： Hong-Chen Cheng ,  Chih-Chieh Chiu ,  Chung-Ji Lu ,  Cheng Hung Lee

IPC: G11C7/00

CPC classification number: G11C7/067 ,  G11C7/12 ,  G11C11/419

Abstract: A memory having a single-ended sensing scheme includes a bit line, a memory cell coupled to the bit line, and a precharge circuit. The precharge circuit is configured to precharge the bit line to a precharge voltage between a power supply voltage and a ground.

Abstract translation: 具有单端感测方案的存储器包括位线，耦合到位线的存储单元和预充电电路。 预充电电路被配置为将位线预充电到电源电压和地之间的预充电电压。

公开(公告)号：US20130096630A1

公开(公告)日：2013-04-18

申请号：US13418668

申请日：2012-03-13

Applicant: Cheng-Hung LEE ,  Chih-Han Chang ,  Chih-Kun Hsiao ,  Kui-Chou Huang ,  Chih-Hui Chen

Inventor： Cheng-Hung LEE ,  Chih-Han Chang ,  Chih-Kun Hsiao ,  Kui-Chou Huang ,  Chih-Hui Chen

IPC: A61B17/80

CPC classification number: A61B17/7283 ,  A61B17/8057 ,  A61B17/8061 ,  A61B17/8605 ,  A61B17/8625

Abstract: An interlocking bone plate system includes an outer bone plate for being arranged outside a broken bone, an inner bone plate for being installed inside the medullary cavity of the broken bone, and screws for being inserted through and engaged with the outer bone plate and the broken bone and then engaged with the inner bone plate so as to interlock the out and inner bone plates together. The inner bone plate provides an added support in addition to the support provided by the outer bone plate, enhancing the structural strength of the whole bone fixation structure and lowering the risk of failed surgery.

Abstract translation: 互锁骨板系统包括用于布置在骨骨外侧的外骨板，用于安装在破骨的髓腔内部的内骨板，以及用于插入并与外骨板接合的螺钉和破碎的骨 骨，然后与内骨板接合，以将外骨板和内骨板互锁在一起。 内骨板除了外骨板提供的支撑外，还增加了支撑，提高了整个骨固定结构的结构强度，降低了手术失败的风险。

公开(公告)号：US08411479B2

公开(公告)日：2013-04-02

申请号：US12835041

申请日：2010-07-13

Applicant: Cheng Hung Lee ,  Jui-Che Tsai ,  Ching-Wei Wu ,  Kuang Ting Chen

Inventor： Cheng Hung Lee ,  Jui-Che Tsai ,  Ching-Wei Wu ,  Kuang Ting Chen

IPC: G11C5/08

CPC classification number: G11C11/41 ,  G11C5/063 ,  G11C8/14 ,  G11C11/412 ,  H01L27/11 ,  H01L27/1104

Abstract: A memory circuit includes a first memory array. The first memory array includes at least one first memory cell for storing a first datum. The at least one first memory cell is coupled with a first word line and a second word line. A second memory array is coupled with the first memory array. The second memory array includes at least one second memory cell for storing a second datum. The at least one second memory cell is coupled with a third word line and a fourth word line. The first word line is coupled with the third word line. The first word line is misaligned from the third word line in a routing direction of the first word line in the first memory array.

Abstract translation: 存储电路包括第一存储器阵列。 第一存储器阵列包括用于存储第一数据的至少一个第一存储器单元。 所述至少一个第一存储单元与第一字线和第二字线耦合。 第二存储器阵列与第一存储器阵列耦合。 第二存储器阵列包括用于存储第二数据的至少一个第二存储器单元。 所述至少一个第二存储单元与第三字线和第四字线耦合。 第一个字线与第三个字线相连。 第一字线在第一存储器阵列中的第一字线的布线方向上与第三字线不对齐。

公开(公告)号：US20130010516A1

公开(公告)日：2013-01-10

申请号：US13178021

申请日：2011-07-07

Applicant: Cheng Hung LEE ,  XiuLi YANG ,  Liangbo ZHUANG

Inventor： Cheng Hung LEE ,  XiuLi YANG ,  Liangbo ZHUANG

IPC: G11C5/06 ,  G06F17/50

CPC classification number: G11C5/06 ,  G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C11/005

Abstract: A semiconductor memory chip that has word lines driven by respective word line drivers and bit lines to carry signals to respective bit line amplifiers/drivers with memory cells at intersections of the word lines and bit lines memory cells. The semiconductor memory chip including various memory cell types, the type of memory cell at an intersection based on a position of the intersection among the word lines and bit lines.

Abstract translation: 一种半导体存储器芯片，其具有由相应的字线驱动器和位线驱动的字线，以将信号传送到具有位线和位线存储器单元的交叉处的存储器单元的各个位线放大器/驱动器。 包括各种存储单元类型的半导体存储器芯片，基于字线和位线之间的交点的位置的交叉路口处的存储单元的类型。

公开(公告)号：US08320163B2

公开(公告)日：2012-11-27

申请号：US12750430

申请日：2010-03-30

Applicant: Cheng Hung Lee

Inventor： Cheng Hung Lee

IPC: G11C11/00 ,  G11C8/16

CPC classification number: G11C8/16 ,  G11C11/412

Abstract: An integrated circuit structure includes a first static random access memory (SRAM) cell including a first read-port and a first write-port; and a second SRAM cell including a second read-port and a second write-port. The first SRAM cell and the second SRAM cell are in a same row and arranged along a row direction. A first word-line is coupled to the first SRAM cell. A second word-line is coupled to the second SRAM cell. A read bit-line is coupled to the first SRAM cell and the second SRAM cell, wherein the read bit-line extends in a column direction perpendicular to the row direction. A write bit-line is coupled to the first SRAM cell and the second SRAM cell.

Abstract translation: 集成电路结构包括包括第一读取端口和第一写入端口的第一静态随机存取存储器（SRAM）单元; 以及包括第二读取端口和第二写入端口的第二SRAM单元。 第一SRAM单元和第二SRAM单元位于同一行中并沿着行方向布置。 第一字线耦合到第一SRAM单元。 第二字线耦合到第二SRAM单元。 读位线耦合到第一SRAM单元和第二SRAM单元，其中读位线在垂直于行方向的列方向上延伸。 写位线耦合到第一SRAM单元和第二SRAM单元。

公开(公告)号：US20120213010A1

公开(公告)日：2012-08-23

申请号：US13030722

申请日：2011-02-18

Applicant: Ching-Wei Wu ,  Kuang Ting Chen ,  Cheng Hung Lee

Inventor： Ching-Wei Wu ,  Kuang Ting Chen ,  Cheng Hung Lee

IPC: G11C7/10 ,  G11C7/06 ,  H01L25/00

CPC classification number: G11C7/08 ,  G11C7/065

Abstract: A circuit includes a first inverter including a first PMOS transistor and a first NMOS transistor, and a second inverter including a second PMOS transistor and a second NMOS transistor. A first node is connected to gates of the first PMOS transistor and the first NMOS transistor and drains of the second PMOS transistor and the second NMOS transistor. A second node is connected to gates of the second PMOS transistor and the second NMOS transistor and drains of the first PMOS transistor and the first NMOS transistor. The circuit further includes a first capacitor having a first capacitance connected to the first node; and a second capacitor having a second capacitance connected to the second node. The second capacitance is greater than the first capacitance.

Abstract translation: 电路包括：第一反相器，包括第一PMOS晶体管和第一NMOS晶体管;以及第二反相器，包括第二PMOS晶体管和第二NMOS晶体管。 第一节点连接到第一PMOS晶体管和第一NMOS晶体管的栅极以及第二PMOS晶体管和第二NMOS晶体管的漏极。 第二节点连接到第二PMOS晶体管和第二NMOS晶体管的栅极以及第一PMOS晶体管和第一NMOS晶体管的漏极。 电路还包括具有连接到第一节点的第一电容的第一电容器; 以及具有连接到第二节点的第二电容的第二电容器。 第二电容大于第一电容。

公开(公告)号：US20120092939A1

公开(公告)日：2012-04-19

申请号：US12917708

申请日：2010-11-02

Applicant: Hong-Chen CHENG ,  Chih-Chieh CHIU ,  Chung-Ji LU ,  Cheng Hung LEE

Inventor： Hong-Chen CHENG ,  Chih-Chieh CHIU ,  Chung-Ji LU ,  Cheng Hung LEE

IPC: G11C7/12 ,  G11C7/06

CPC classification number: G11C7/067 ,  G11C7/12 ,  G11C11/419

Abstract: A memory having a single-ended sensing scheme includes a bit line, a memory cell coupled to the bit line, and a precharge circuit. The precharge circuit is configured to precharge the bit line to a precharge voltage between a power supply voltage and a ground.

Abstract translation: 具有单端感测方案的存储器包括位线，耦合到位线的存储单元和预充电电路。 预充电电路被配置为将位线预充电到电源电压和地之间的预充电电压。

公开(公告)号：US20120061764A1

公开(公告)日：2012-03-15

申请号：US12879447

申请日：2010-09-10

Applicant: Annie LUM ,  Derek C. TAO ,  Cheng Hung LEE ,  Chung-Ji LU ,  Hong-Chen CHENG ,  Vineet Kumar AGRAWAL ,  Keun-Young KIM ,  Pyong Yun CHO

Inventor： Annie LUM ,  Derek C. TAO ,  Cheng Hung LEE ,  Chung-Ji LU ,  Hong-Chen CHENG ,  Vineet Kumar AGRAWAL ,  Keun-Young KIM ,  Pyong Yun CHO

IPC: H01L27/088 ,  G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/5081 ,  G06F2217/12 ,  H01L27/0207 ,  H01L27/088 ,  Y02P90/265

Abstract: The layouts, device structures, and methods described above utilize dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures to the dummy device. Such extension of diffusion regions resolves or reduces LOD and edge effect issues. In addition, treating the gate structure of a dummy device next to an edge device also allows only one dummy structure to be added next to the dummy device and saves the real estate on the semiconductor chip. The dummy devices are deactivated and their performance is not important. Therefore, utilizing dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures according to design rules allows the resolution or reduction or LOD and edge effect issues without the penalty of yield reduction or increase in layout areas.

Abstract translation: 上述布局，装置结构和方法利用虚设装置将边缘结构和/或非允许结构的扩散区域扩展到虚设装置。 这种扩散区域的扩展可解决或减少LOD和边缘效应问题。 此外，在边缘装置旁边处理伪装置的栅极结构也仅允许在虚设装置旁边添加一个虚拟结构，并将该不动产保存在半导体芯片上。 虚拟设备被禁用，其性能不重要。 因此，利用虚设装置根据设计规则扩展边缘结构和/或非允许结构的扩散区域允许分辨率或降低或LOD和边缘效应发生，而不会降低成品率或增加布局面积。

公开(公告)号：US20120020179A1

公开(公告)日：2012-01-26

申请号：US12839490

申请日：2010-07-20

Applicant: You-Cheng XIAO ,  Hong-Chen CHENG ,  Chung-Ji LU ,  Cheng Hung LEE ,  Jung-Hsuan CHEN ,  Li-Chun TIEN

Inventor： You-Cheng XIAO ,  Hong-Chen CHENG ,  Chung-Ji LU ,  Cheng Hung LEE ,  Jung-Hsuan CHEN ,  Li-Chun TIEN

IPC: G11C8/10

CPC classification number: G11C8/10 ,  G11C11/413

Abstract: A word line decoder comprises a plurality of driver circuits, a plurality of word lines provided at respective outputs of the driver circuits, and a plurality of primary input lines coupled to the driver circuits and oriented in a first direction. The word line decoder also comprises a plurality of secondary input lines coupled to the driver circuits and oriented in the first direction. The word line decoder also comprises a local decode line coupled to each of the primary input lines. The word line decoder also comprises a decode line coupled to the local decode line and oriented in the first direction. A cluster decode line is coupled to the decode line. The word line decoder is configured to select at least one of the word lines based on signals provided by the cluster decode line and the secondary input lines.

Abstract translation: 字线解码器包括多个驱动器电路，设置在驱动器电路的各个输出处的多个字线以及耦合到驱动器电路并沿第一方向取向的多个主输入线。 字线解码器还包括耦合到驱动器电路并沿第一方向定向的多个次级输入线。 字线解码器还包括耦合到每个主输入线的本地解码线。 字线解码器还包括耦合到本地解码线并沿第一方向定向的解码线。 集群解码线耦合到解码线。 字线解码器被配置为基于由群集解码线和辅助输入线提供的信号来选择至少一个字线。

公开(公告)号：US20120020176A1

公开(公告)日：2012-01-26

申请号：US12839575

申请日：2010-07-20

Applicant: Chung-Ji Lu ,  Hung-Jen Liao ,  Cheng Hung Lee ,  Derek C. Tao ,  Annie-Li-Keow Lum ,  Hong-Chen Cheng

Inventor： Chung-Ji Lu ,  Hung-Jen Liao ,  Cheng Hung Lee ,  Derek C. Tao ,  Annie-Li-Keow Lum ,  Hong-Chen Cheng

IPC: G11C7/06 ,  H03F3/45

CPC classification number: G11C7/067 ,  G11C7/065

Abstract: Some embodiments regard a circuit comprising: a first left transistor having a first left drain, a first left gate, and a first left source; a second left transistor having a second left drain, a second left gate, and a second left source; a third left transistor having a third left drain, a third left gate, and a third left source; a first right transistor having a first right drain, a first right gate, and a first right source; a second right transistor having a second right drain, a second right gate, and a second right source; a third right transistor having a third right drain, a third right gate, and a third right source; a left node electrically coupling the first left drain, the second left drain, the second left gate, the third right gate, and the third left drain; and a right node electrically coupling the first right drain, the second right drain, the second right gate, the third left gate, and the third right drain.

Abstract translation: 一些实施例涉及一种电路，包括：具有第一左漏极，第一左栅极和第一左源的第一左晶体管; 第二左晶体管，具有第二左漏极，第二左栅极和第二左源极; 第三左晶体管，具有第三左漏极，第三左栅极和第三左源; 第一右晶体管，具有第一右漏极，第一右栅极和第一右源; 第二右晶体管，具有第二右漏极，第二右栅极和第二右源; 第三右晶体管，具有第三右漏极，第三右栅极和第三右源; 左节点，电耦合第一左排水口，第二左排水管，第二左闸门，第三右闸门和第三左排水管; 以及电连接第一右排水管，第二右排水管，第二右浇口，第三左浇口和第三右排水沟的右节点。