公开(公告)号：US20120092939A1

公开(公告)日：2012-04-19

申请号：US12917708

申请日：2010-11-02

申请人： Hong-Chen CHENG ,  Chih-Chieh CHIU ,  Chung-Ji LU ,  Cheng Hung LEE

发明人： Hong-Chen CHENG ,  Chih-Chieh CHIU ,  Chung-Ji LU ,  Cheng Hung LEE

IPC分类号： G11C7/12 ,  G11C7/06

CPC分类号： G11C7/067 ,  G11C7/12 ,  G11C11/419

摘要： A memory having a single-ended sensing scheme includes a bit line, a memory cell coupled to the bit line, and a precharge circuit. The precharge circuit is configured to precharge the bit line to a precharge voltage between a power supply voltage and a ground.

摘要翻译： 具有单端感测方案的存储器包括位线，耦合到位线的存储单元和预充电电路。 预充电电路被配置为将位线预充电到电源电压和地之间的预充电电压。

公开(公告)号：US20120195139A1

公开(公告)日：2012-08-02

申请号：US13443619

申请日：2012-04-10

申请人： Hsu-Shun CHEN ,  Cheng Hung LEE ,  Chung-Ji LU ,  Hong-Chen CHENG ,  Chung-Yi WU ,  Chih-Chieh CHIU

发明人： Hsu-Shun CHEN ,  Cheng Hung LEE ,  Chung-Ji LU ,  Hong-Chen CHENG ,  Chung-Yi WU ,  Chih-Chieh CHIU

IPC分类号： G11C7/00 ,  G11C5/14

CPC分类号： G11C7/1048 ,  G11C5/14

摘要： In some embodiments related to a memory array, a sense amplifier (SA) uses a first power supply, e.g., voltage VDDA, while other circuitry, e.g., signal output logic, uses a second power supply, e.g., voltage VDDB. Various embodiments place the SA and a pair of transferring devices at a local IO row, and a voltage keeper at the main IO section of the same memory array. The SA, the transferring devices, and the voltage keeper, when appropriate, operate together so that the data logic of the circuitry provided by voltage VDDB is the same as the data logic of the circuitry provided by voltage VDDA.

摘要翻译： 在与存储器阵列相关的一些实施例中，读出放大器（SA）使用第一电源，例如电压VDDA，而其它电路（例如，信号输出逻辑）使用第二电源，例如电压VDDB。 各种实施例将SA和一对传送装置放置在本地IO行上，并将电压保持器放置在同一存储器阵列的主IO部分。 SA，传输装置和电压保持器在适当的情况下一起工作，使得由电压VDDB提供的电路的数据逻辑与由电压VDDA提供的电路的数据逻辑相同。

公开(公告)号：US20120182792A1

公开(公告)日：2012-07-19

申请号：US13008992

申请日：2011-01-19

申请人： Hong-Chen CHENG ,  Chih-Chieh CHIU ,  Hsu-Shun CHEN ,  Chung-Ji LU ,  Cheng-Hung LEE ,  Hung-Jen LIAO

发明人： Hong-Chen CHENG ,  Chih-Chieh CHIU ,  Hsu-Shun CHEN ,  Chung-Ji LU ,  Cheng-Hung LEE ,  Hung-Jen LIAO

IPC分类号： G11C11/413 ,  G11C5/14

CPC分类号： G11C11/413

摘要： A SRAM system includes: a SRAM cell array coupled between high and low supply nodes, a difference therebetween defining a data retention voltage (VDR) for a low power data retention mode; a main power switch coupling one of high and low supply nodes to a main power supply and disconnecting the one high and low supply nodes from the main power supply during the low power data retention mode; a monitor cell including a SRAM cell preloaded with a data bit and configured for data destruction responsive to a reduction in VDR before data destruction occurs in the SRAM cell array; and a clamping power switch responsive to data destruction in the monitor cell to couple the one of the high and low supply nodes to the main power supply.

摘要翻译： SRAM系统包括：耦合在高电源节点和低电源节点之间的SRAM单元阵列，其间限定用于低功率数据保持模式的数据保持电压（VDR）; 主电源开关将高电源和低电源节点之一耦合到主电源，并且在低功率数据保持模式期间将一个高电源和低电源节点与主电源断开; 监控单元，其包括预先装载有数据位的SRAM单元，并且被配置为在SRAM单元阵列中发生数据破坏之前响应于VDR的减小而进行的数据破坏; 以及钳位电源开关，其响应于监视器单元中的数据破坏，将高电源节点和低电源节点中的一个耦合到主电源。

公开(公告)号：US20130208533A1

公开(公告)日：2013-08-15

申请号：US13372099

申请日：2012-02-13

申请人： Jung-Ping YANG ,  Hong-Chen CHENG ,  Chih-Chieh CHIU ,  Chia-En HUANG ,  Cheng Hung LEE

发明人： Jung-Ping YANG ,  Hong-Chen CHENG ,  Chih-Chieh CHIU ,  Chia-En HUANG ,  Cheng Hung LEE

IPC分类号： G11C11/40 ,  G11C7/12 ,  G11C7/00

CPC分类号： G11C11/4094 ,  G11C11/419

摘要： A memory includes a first bit line, a memory cell coupled to the first bit line, and a read assist device coupled to the first bit line. The read assist device is configured to pull a first voltage on the first bit line toward a predetermined voltage in response to a first datum being read out from the memory cell. The read assist device includes a first circuit configured to establish a first current path between the first bit line and a node of the predetermined voltage during a first stage. The read assist device further includes a second circuit configured to establish a second current path between the first bit line and the node of the predetermined voltage during a second, subsequent stage.

摘要翻译： 存储器包括第一位线，耦合到第一位线的存储器单元和耦合到第一位线的读取辅助器件。 读取辅助装置被配置为响应于从存储器单元读出的第一数据，将第一位线上的第一电压拉向预定电压。 读取辅助装置包括第一电路，其被配置为在第一阶段期间在第一位线和预定电压的节点之间建立第一电流路径。 读取辅助装置还包括第二电路，其被配置为在第二后续阶段期间在第一位线和预定电压的节点之间建立第二电流路径。

公开(公告)号：US20130194877A1

公开(公告)日：2013-08-01

申请号：US13362847

申请日：2012-01-31

申请人： Jung-Ping YANG ,  Hong-Chen CHENG ,  Chih-Chieh CHIU ,  Chia-En HUANG ,  Cheng Hung LEE

发明人： Jung-Ping YANG ,  Hong-Chen CHENG ,  Chih-Chieh CHIU ,  Chia-En HUANG ,  Cheng Hung LEE

IPC分类号： G11C7/06 ,  G11C7/10

CPC分类号： G11C7/12 ,  G11C7/106 ,  G11C7/1087 ,  G11C7/18 ,  G11C11/419 ,  G11C2207/005

摘要： A memory includes a plurality of memory blocks, a plurality of global bit lines, a common pre-charging circuit, and a selection circuit. Each memory block includes a pair of bit lines, and a plurality of memory cells coupled to the pair of bit lines. Each global bit line is coupled to at least one of the memory blocks. The pre-charging circuit is configured to pre-charge the global bit lines, one at a time, to a pre-charge voltage. The selection circuit is coupled between the pre-charging circuit and the global bit lines, and configured to couple the global bit lines, one at a time, to the pre-charging circuit.

摘要翻译： 存储器包括多个存储器块，多个全局位线，公共预充电电路和选择电路。 每个存储块包括一对位线和耦合到该对位线的多个存储器单元。 每个全局位线耦合到至少一个存储器块。 预充电电路被配置为将全局位线一次一个地预充电到预充电电压。 选择电路耦合在预充电电路和全局位线之间，并且被配置为将全局位线一次一个地耦合到预充电电路。

公开(公告)号：US20120061764A1

公开(公告)日：2012-03-15

申请号：US12879447

申请日：2010-09-10

申请人： Annie LUM ,  Derek C. TAO ,  Cheng Hung LEE ,  Chung-Ji LU ,  Hong-Chen CHENG ,  Vineet Kumar AGRAWAL ,  Keun-Young KIM ,  Pyong Yun CHO

发明人： Annie LUM ,  Derek C. TAO ,  Cheng Hung LEE ,  Chung-Ji LU ,  Hong-Chen CHENG ,  Vineet Kumar AGRAWAL ,  Keun-Young KIM ,  Pyong Yun CHO

IPC分类号： H01L27/088 ,  G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5081 ,  G06F2217/12 ,  H01L27/0207 ,  H01L27/088 ,  Y02P90/265

摘要： The layouts, device structures, and methods described above utilize dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures to the dummy device. Such extension of diffusion regions resolves or reduces LOD and edge effect issues. In addition, treating the gate structure of a dummy device next to an edge device also allows only one dummy structure to be added next to the dummy device and saves the real estate on the semiconductor chip. The dummy devices are deactivated and their performance is not important. Therefore, utilizing dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures according to design rules allows the resolution or reduction or LOD and edge effect issues without the penalty of yield reduction or increase in layout areas.

摘要翻译： 上述布局，装置结构和方法利用虚设装置将边缘结构和/或非允许结构的扩散区域扩展到虚设装置。 这种扩散区域的扩展可解决或减少LOD和边缘效应问题。 此外，在边缘装置旁边处理伪装置的栅极结构也仅允许在虚设装置旁边添加一个虚拟结构，并将该不动产保存在半导体芯片上。 虚拟设备被禁用，其性能不重要。 因此，利用虚设装置根据设计规则扩展边缘结构和/或非允许结构的扩散区域允许分辨率或降低或LOD和边缘效应发生，而不会降低成品率或增加布局面积。

公开(公告)号：US20120020179A1

公开(公告)日：2012-01-26

申请号：US12839490

申请日：2010-07-20

申请人： You-Cheng XIAO ,  Hong-Chen CHENG ,  Chung-Ji LU ,  Cheng Hung LEE ,  Jung-Hsuan CHEN ,  Li-Chun TIEN

发明人： You-Cheng XIAO ,  Hong-Chen CHENG ,  Chung-Ji LU ,  Cheng Hung LEE ,  Jung-Hsuan CHEN ,  Li-Chun TIEN

IPC分类号： G11C8/10

CPC分类号： G11C8/10 ,  G11C11/413

摘要： A word line decoder comprises a plurality of driver circuits, a plurality of word lines provided at respective outputs of the driver circuits, and a plurality of primary input lines coupled to the driver circuits and oriented in a first direction. The word line decoder also comprises a plurality of secondary input lines coupled to the driver circuits and oriented in the first direction. The word line decoder also comprises a local decode line coupled to each of the primary input lines. The word line decoder also comprises a decode line coupled to the local decode line and oriented in the first direction. A cluster decode line is coupled to the decode line. The word line decoder is configured to select at least one of the word lines based on signals provided by the cluster decode line and the secondary input lines.

摘要翻译： 字线解码器包括多个驱动器电路，设置在驱动器电路的各个输出处的多个字线以及耦合到驱动器电路并沿第一方向取向的多个主输入线。 字线解码器还包括耦合到驱动器电路并沿第一方向定向的多个次级输入线。 字线解码器还包括耦合到每个主输入线的本地解码线。 字线解码器还包括耦合到本地解码线并沿第一方向定向的解码线。 集群解码线耦合到解码线。 字线解码器被配置为基于由群集解码线和辅助输入线提供的信号来选择至少一个字线。

公开(公告)号：US20130010560A1

公开(公告)日：2013-01-10

申请号：US13535075

申请日：2012-06-27

申请人： Chung-Ji LU ,  Hung-Jen LIAO ,  Cheng Hung LEE ,  Derek C. TAO ,  Annie-Li-Keow LUM ,  Hong-Chen CHENG

发明人： Chung-Ji LU ,  Hung-Jen LIAO ,  Cheng Hung LEE ,  Derek C. TAO ,  Annie-Li-Keow LUM ,  Hong-Chen CHENG

IPC分类号： H03F3/45 ,  G11C7/06

CPC分类号： G11C7/067 ,  G11C7/065

摘要： A circuit includes a first node, a second node, a first current mirror circuit, and a second current minor circuit. The first current mirror circuit has a reference end and a mirrored end. The reference end of the first current minor circuit is coupled to the first node, and the mirrored end of the first current minor circuit is coupled to the second node. The second current minor circuit has a reference end and a mirrored end. The reference end of the second current minor circuit is coupled to the second node, and the mirrored end of the second current minor circuit is coupled to the first node.

摘要翻译： 电路包括第一节点，第二节点，第一电流镜电路和第二电流次要电路。 第一电流镜电路具有参考端和镜像端。 第一当前次要电路的参考端耦合到第一节点，并且第一当前次要电路的镜像端耦合到第二节点。 第二个当前次级电路具有参考端和镜像端。 第二电流次级电路的参考端耦合到第二节点，并且第二电流次级电路的镜像端耦合到第一节点。

公开(公告)号：US20140036608A1

公开(公告)日：2014-02-06

申请号：US13776040

申请日：2013-02-25

申请人： Chih-Chieh CHIU ,  Hong-Chen CHENG

发明人： Chih-Chieh CHIU ,  Hong-Chen CHENG

IPC分类号： G11C7/22

CPC分类号： G11C11/419 ,  G11C7/08 ,  G11C7/227 ,  G11C11/4076 ,  G11C11/4099

摘要： A signal generating circuit includes a first circuit, a tracking circuit, and a delay circuit coupled with the first circuit and the tracking circuit. The first circuit is configured to receive a first clock signal and an output signal from an output of the delay circuit and to generate a second clock signal and at least one first tracking signal. The tracking circuit is configured to receive the at least one first tracking signal and to generate a second tracking signal. The delay circuit is configured to receive the second clock signal and the second tracking signal and to generate the output signal.

摘要翻译： 信号发生电路包括第一电路，跟踪电路和与第一电路和跟踪电路耦合的延迟电路。 第一电路被配置为从延迟电路的输出接收第一时钟信号和输出信号，并且产生第二时钟信号和至少一个第一跟踪信号。 跟踪电路被配置为接收至少一个第一跟踪信号并产生第二跟踪信号。 延迟电路被配置为接收第二时钟信号和第二跟踪信号并产生输出信号。

公开(公告)号：US20130128655A1

公开(公告)日：2013-05-23

申请号：US13303231

申请日：2011-11-23

申请人： Hong-Chen CHENG ,  Chia-En HUANG ,  Chih-Chieh CHIU ,  Jung-Ping YANG

发明人： Hong-Chen CHENG ,  Chia-En HUANG ,  Chih-Chieh CHIU ,  Jung-Ping YANG

IPC分类号： G11C11/34 ,  H03L5/00

CPC分类号： G11C8/10 ,  G11C11/413 ,  G11C11/418

摘要： An apparatus includes a level shifter and a switching circuit. The level shifter includes an input, a first output, and second output having a logic value complementary to a logic value of the first output. The switching circuit includes a data input, a feedback input coupled to the second output of the level shifter, and an output coupled to the input of the level shifter. The switching circuit is configured to selectively latch, based on a select signal, a logic state of the level shifter at the second output.

摘要翻译： 一种装置包括电平移位器和开关电路。 电平移位器包括具有与第一输出的逻辑值互补的逻辑值的输入，第一输出和第二输出。 切换电路包括数据输入，耦合到电平移位器的第二输出的反馈输入以及耦合到电平移位器的输入的输出。 开关电路被配置为基于选择信号选择性地锁存第二输出处的电平移位器的逻辑状态。