公开(公告)号：US07791391B2

公开(公告)日：2010-09-07

申请号：US12215829

申请日：2008-06-30

申请人： Dae-Kun Yoon ,  Dae-Han Kwon ,  Taek-Sang Song

发明人： Dae-Kun Yoon ,  Dae-Han Kwon ,  Taek-Sang Song

IPC分类号： H03K5/13

CPC分类号： H03L7/0814 ,  H03K2005/00286 ,  H03L7/087

摘要： A quadrature phase correction circuit includes an N-bit code counter configured to generate an N-bit code value according to a detected phase difference when a quadrature phase correction is carried out, N-bit code values are stored according to a plurality of detected phase differences. A controller shares the N-bit code counter, controls the generation of the N-bit code values according to the plurality of detected phase differences, and controls the storing of the N-bit code values in an allocated space of the storage by use of a multiplexer configured to provide the plurality of detected phase differences to the N-bit code counter, and a demultiplexer configured to store the N-bit code values in the allocated space of the storage.

摘要翻译： 正交相位校正电路包括N比特码计数器，被配置为当执行正交相位校正时根据检测到的相位差产生N比特码值，根据多个检测相位存储N比特码值 差异 A控制器共享N位代码计数器，根据多个检测到的相位差控制N位代码值的产生，并且通过使用N位代码值来存储N位代码值到存储器的分配空间中 多路复用器，被配置为向N位代码计数器提供多个检测到的相位差，以及解复用器，被配置为将N位代码值存储在存储器的分配空间中。

公开(公告)号：US20090322399A1

公开(公告)日：2009-12-31

申请号：US12325346

申请日：2008-12-01

申请人： Dae-Han KWON ,  Taek-Sang SONG

发明人： Dae-Han KWON ,  Taek-Sang SONG

IPC分类号： G06F1/06

CPC分类号： G06F1/06

摘要： A clock generating circuit, including a pulse generating unit to generate a plurality of pulse signals based on a reference clock, the pulse signals each having the same period, a phase difference between the adjacent pulse signals being a first phase difference; and a multi-phase clock generating unit to generate a plurality of multi-phase clocks, a phase difference between the adjacent multi-phase clocks being equal to a second phase difference between pulse signals of a pulse signal pair, based on a plurality of unit-phase clock generating units receiving the pulse signal pairs.

摘要翻译： 一种时钟发生电路，包括：脉冲发生单元，用于基于参考时钟产生多个脉冲信号;每个脉冲信号具有相同的周期;相邻脉冲信号之间的相位差是第一相位差; 以及多相时钟发生单元，用于生成多个多相时钟，相邻的多相时钟之间的相位差等于脉冲信号对的脉冲信号之间的第二相位差，基于多个单位 接收脉冲信号对的相位时钟发生单元。

公开(公告)号：US20090160560A1

公开(公告)日：2009-06-25

申请号：US12079443

申请日：2008-03-26

申请人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

发明人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

IPC分类号： H03L7/00

CPC分类号： H03L7/0893 ,  H03L7/0896 ,  H03L7/0898

摘要： Phase locked loop and method for controlling the same includes a phase/frequency detector configured to detect a phase difference between an input clock and a feedback clock to generate an up signal or a down signal depending on the detected phase difference, a charge pump configured to variably control a bandwidth according to a bandwidth control signal input thereinto, the charge pump operating in response to the up signal or the down signal and a voltage controlled oscillator configured to change a frequency according to an output of the charge pump.

摘要翻译： 锁相环及其控制方法包括相位/频率检测器，被配置为检测输入时钟和反馈时钟之间的相位差，以根据检测到的相位差产生上升信号或下降信号，电荷泵被配置为 根据其中输入的带宽控制信号可变地控制带宽，所述电荷泵响应于上升信号或下降信号而工作;以及压控振荡器，被配置为根据电荷泵的输出来改变频率。

公开(公告)号：US20090160510A1

公开(公告)日：2009-06-25

申请号：US12157235

申请日：2008-06-09

申请人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Dae-Kun Yoon

发明人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Dae-Kun Yoon

IPC分类号： H03L7/06 ,  H03K3/01

CPC分类号： H03L7/0893 ,  H03L7/099 ,  H03L7/107 ,  H03L2207/06

摘要： Bias voltage generator circuit and clock synchronizing circuit includes a bias unit configured to control a current in response to a bandwidth control signal, an amplification unit configured to differentially amplify an input signal in response to the current controlled by the bias unit and an output unit configured to receive an output signal of the amplification unit to output the bias voltage.

摘要翻译： 偏置电压发生器电路和时钟同步电路包括被配置为响应于带宽控制信号来控制电流的偏置单元，被配置为响应于由偏置单元控制的电流差异放大输入信号的放大单元和配置的输出单元 以接收放大单元的输出信号以输出偏置电压。

公开(公告)号：US20090115467A1

公开(公告)日：2009-05-07

申请号：US12005515

申请日：2007-12-27

申请人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Dae-Kun Yoon ,  Taek-Sang Song

发明人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Dae-Kun Yoon ,  Taek-Sang Song

IPC分类号： H03B19/00 ,  G06F1/06

CPC分类号： G06F1/06

摘要： A semiconductor memory device can optimize the layout area and current consumption based on multi-phase clock signals which are generated by dividing a source clock signal using a reset signal without a delay locked loop and a phase locked loop in order to have various phase information of low frequencies and different activation timings with a constant phase difference.

摘要翻译： 半导体存储器件可以基于多相时钟信号来优化布局面积和电流消耗，该多相时钟信号是通过使用没有延迟锁定环路和锁相环路的复位信号对源时钟信号进行分频而产生的，以便具有 低频和不同的激活时序具有恒定的相位差。

公开(公告)号：US20090115459A1

公开(公告)日：2009-05-07

申请号：US12005564

申请日：2007-12-27

申请人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Dae-Kun Yoon ,  Taek-Sang Song

发明人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Dae-Kun Yoon ,  Taek-Sang Song

IPC分类号： H03K3/017 ,  H03K5/125

CPC分类号： H03K5/1565

摘要： A semiconductor device includes a pulse signal generating unit for generating a plurality of pulse signals each of which has a different pulse width from each other, a signal multiplexing unit for outputting one of the plurality of the pulse signals as an enable signal in response to an operating frequency of the semiconductor device, and a duty ratio detecting unit for detecting a duty ratio of external clock signals in response to the enable signal.

摘要翻译： 一种半导体器件，包括：脉冲信号产生单元，用于产生彼此具有不同脉冲宽度的多个脉冲信号;信号复用单元，用于响应于一个或多个脉冲信号输出多个脉冲信号中的一个作为使能信号 半导体器件的工作频率以及响应于使能信号检测外部时钟信号的占空比的占空比检测单元。

公开(公告)号：US07512823B2

公开(公告)日：2009-03-31

申请号：US11109270

申请日：2005-04-19

申请人： Dae Han Kwon

发明人： Dae Han Kwon

IPC分类号： G06F1/26

CPC分类号： G11C5/147

摘要： Disclosed is a semiconductor device capable of detecting levels of an external supply voltage, which includes a plurality of signal receivers for simultaneously receiving external input signals, wherein a driving voltage is applied to only one of the signal receivers according to the levels of the external supply voltage.

摘要翻译： 公开了能够检测外部电源电压的水平的半导体器件，其包括用于同时接收外部输入信号的多个信号接收器，其中驱动电压仅根据外部电源的电平被施加到信号接收器中的一个 电压。

公开(公告)号：US20070237019A1

公开(公告)日：2007-10-11

申请号：US11646351

申请日：2006-12-28

申请人： Dae Han Kwon

发明人： Dae Han Kwon

IPC分类号： G11C8/00

CPC分类号： G11C7/1051 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/106 ,  G11C7/1066 ,  G11C2207/108

摘要： The data output circuit for a semiconductor memory apparatus includes a plurality of pads in which a range of use is determined such that the respective pads are used exclusively in each of at least two kinds of unit data output modes or used commonly in all of the at least two kinds of unit data output modes, a plurality of data lines that transmit data from a plurality of memory banks to the outside of the memory banks, and a data output control unit that outputs data from a data line among the plurality of data lines, according to at least one control signal, to a signal line corresponding to a pad used in a currently set unit data output mode among the plurality of pads.

摘要翻译： 用于半导体存储装置的数据输出电路包括多个焊盘，其中确定使用范围使得各个焊盘仅用于至少两种单元数据输出模式中的每一种，或者通常用于所有的 至少两种单位数据输出模式，将数据从多个存储体传输到存储体的外部的多条数据线;以及数据输出控制单元，其从多条数据线中的数据线输出数据 根据至少一个控制信号，对应于在多个焊盘中当前设置的单位数据输出模式中使用的焊盘的信号线。

公开(公告)号：US20060139984A1

公开(公告)日：2006-06-29

申请号：US11109270

申请日：2005-04-19

申请人： Dae Han Kwon

发明人： Dae Han Kwon

IPC分类号： G11C5/00

CPC分类号： G11C5/147

摘要： Disclosed is a semiconductor device capable of detecting levels of an external supply voltage, which includes a plurality of signal receivers for simultaneously receiving external input signals, wherein a driving voltage is applied to only one of the signal receivers according to the levels of the external supply voltage.

摘要翻译： 公开了能够检测外部电源电压的水平的半导体器件，其包括用于同时接收外部输入信号的多个信号接收器，其中驱动电压仅根据外部电源的电平施加到信号接收器中的一个 电压。

公开(公告)号：US08542044B2

公开(公告)日：2013-09-24

申请号：US13334241

申请日：2011-12-22

申请人： Yong-Ju Kim ,  Dae-Han Kwon ,  Hae-Rang Choi ,  Jae-Min Jang

发明人： Yong-Ju Kim ,  Dae-Han Kwon ,  Hae-Rang Choi ,  Jae-Min Jang

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  G11C7/222 ,  G11C11/40 ,  G11C29/023 ,  G11C2029/0409

摘要： A semiconductor integrated circuit includes: a delay locked loop (DLL) configured to generate a DLL clock signal by delaying a source clock signal by a first delay time for obtaining a lock, wherein an update period of the DLL is controlled in response to an update period control signal after locking is completed; and an update period controller configured to generate the update period control signal based on a second delay time occurring in a loop path of the DLL in response to the source clock signal and a plurality of control signals provided from the DLL.

摘要翻译： 半导体集成电路包括：延迟锁定环（DLL），被配置为通过将源时钟信号延迟第一延迟时间来获得锁定来产生DLL时钟信号，其中响应于更新来控制DLL的更新周期 锁定后的周期控制信号完成; 以及更新周期控制器，被配置为响应于源时钟信号和从DLL提供的多个控制信号，基于在DLL的循环路径中出现的第二延迟时间来生成更新周期控制信号。