公开(公告)号：US07868369B2

公开(公告)日：2011-01-11

申请号：US12276152

申请日：2008-11-21

Applicant: Donald L. Yates ,  Garry A. Mercaldi

Inventor： Donald L. Yates ,  Garry A. Mercaldi

IPC: H01L27/108

CPC classification number: H01L28/92 ,  G03F7/0035 ,  G03F7/201 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/0275 ,  H01L21/32139 ,  H01L27/10852 ,  H01L28/84 ,  H01L28/91

Abstract: Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical planarization (CMP), thus eliminating CMP-induced defects and variations. The methods utilize localized masking of holes for protection of the inside of the holes during non-mechanical removal of exposed surface layers. The localized masking is accomplished through differential exposure of a resist layer to electromagnetic or thermal energy. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract translation: 用于集成电路的容器结构及其制造方法，而不使用机械平面化（例如化学机械平面化（CMP）），从而消除了CMP引起的缺陷和变化。 该方法利用在非机械去除暴露的表面层期间的孔的局部掩蔽来保护孔的内部。 通过将抗蚀剂层与电磁或热能的差分曝光来实现局部掩蔽。 容器结构适用于并入这种存储单元的存储器单元和装置以及其它集成电路。

公开(公告)号：US07582570B2

公开(公告)日：2009-09-01

申请号：US11312110

申请日：2005-12-20

Applicant: Donald L. Yates

Inventor： Donald L. Yates

IPC: H01L21/302

CPC classification number: H01L21/02071 ,  H01L21/02052 ,  H01L21/31116 ,  H01L21/31133 ,  H01L21/32136 ,  H01L43/12

Abstract: A composition and methods for using the composition in removing processing byproducts is provided. The composition can be non-aqueous or semi-aqueous. The non-aqueous composition includes a non-aqueous solvent and one or more components including a fluoride compound and a pyridine compound. The semi-aqueous composition includes glacial acetic acid and one or more components including a fluoride compound and a pyridine compound. The composition can be used in removing processing byproducts from substrate assembly, including MRAM devices, that include at least a metal containing region and processing byproducts, where removing the processing byproducts includes exposing the substrate assembly to the composition for a time effective to remove at least a portion of the processing byproducts.

Abstract translation: 提供了组合物和使用该组合物去除加工副产物的方法。 组合物可以是非水或半水性的。 非水性组合物包括非水溶剂和一种或多种包含氟化物和吡啶化合物的组分。 半水性组合物包括冰醋酸和一种或多种组分，包括氟化物和吡啶化合物。 该组合物可用于从包括至少含金属区域和加工副产物的基片组装（包括MRAM器件）中除去加工副产物，其中除去加工副产物包括将基片组件暴露于组合物上一段时间以有效地除去至少 一部分加工副产品。

公开(公告)号：US07573121B2

公开(公告)日：2009-08-11

申请号：US11514694

申请日：2006-08-31

Applicant: Donald L Yates ,  Garry A Mercaldi ,  James J Hofmann

Inventor： Donald L Yates ,  Garry A Mercaldi ,  James J Hofmann

IPC: H01L29/94

CPC classification number: H01L27/1085 ,  H01L27/10852 ,  H01L28/65 ,  H01L28/82 ,  H01L28/84 ,  H01L28/91

Abstract: Methods for forming the lower electrode of a capacitor in a semiconductor circuit, and the capacitors formed by such methods are provided. The lower electrode is fabricated by forming a texturizing underlayer and then depositing a conductive material thereover. In one embodiment of a method of forming the lower electrode, the texturizing layer is formed by depositing a polymeric material comprising a hydrocarbon block and a silicon-containing block, over the insulative layer of a container, and then subsequently converting the polymeric film to relief or porous nanostructures by exposure to UV radiation and ozone, resulting in a textured porous or relief silicon oxycarbide film. A conductive material is then deposited over the texturizing layer resulting in a lower electrode have an upper roughened surface. In another embodiment of a method of forming the lower electrode, the texturizing underlayer is formed by depositing overlying first and second conductive metal layers and annealing the metal layers to form surface dislocations, preferably structured as a periodic network. A conductive metal is then deposited in gaseous phase, and agglomerates onto the surface dislocations of the texturizing layer, forming nanostructures in the form of island clusters. The capacitor is completed by depositing a dielectric layer over the formed lower electrode, and forming an upper capacitor electrode over the dielectric layer. The capacitors are particularly useful in fabricating DRAM cells.

Abstract translation: 提供了形成半导体电路中的电容器的下电极的方法以及通过这些方法形成的电容器。 下电极通过形成纹理化的底层然后在其上沉积导电材料来制造。 在形成下电极的方法的一个实施方案中，通过在容器的绝缘层上沉积包含烃嵌段和含硅嵌段的聚合材料，然后随后将聚合物膜转化为浮雕而形成该组织化层 或通过暴露于UV辐射和臭氧的多孔纳米结构，导致织构化的多孔或缓蚀硅碳化硅膜。 然后将导电材料沉积在纹理化层上，导致下部电极具有上部粗糙表面。 在形成下电极的方法的另一实施例中，通过沉积覆盖的第一和第二导电金属层并退火金属层形成优选构造为周期性网络的表面位错来形成纹理化下层。 然后将导电金属沉积在气相中，并且聚集到构造层的表面位错上，形成岛簇形式的纳米结构。 电容器通过在形成的下电极上沉积介电层并在电介质层上形成上电容器电极来完成。 电容器在制造DRAM单元时特别有用。

公开(公告)号：US07521373B2

公开(公告)日：2009-04-21

申请号：US10889084

申请日：2004-07-12

Applicant: Donald L Yates

Inventor： Donald L Yates

IPC: H01L21/302

CPC classification number: C09K13/08 ,  B08B3/08 ,  C09K13/00 ,  C09K13/04 ,  C09K13/06 ,  C11D7/08 ,  C11D7/10 ,  C11D7/50 ,  C11D11/0047 ,  C23G1/02 ,  G03F7/423 ,  H01L21/31111 ,  H01L21/31133 ,  Y10S438/948

Abstract: An improved composition and method for cleaning the surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k dielectric material such as silicon dioxide, a photoresist layer overlying a low-k dielectric layer, or both layers from the surface of a wafer. The composition is formulated according to the invention to provide a desired removal rate of the low-k dielectric and/or photoresist from the surface of the wafer. By varying the fluorine ion component, and the amounts of the fluorine ion component and acid, component, and controlling the pH, a composition can be formulated in order to achieve a desired low-k dielectric removal rate that ranges from slow and controlled at about 50 to about 1000 angstroms per minute, to a relatively rapid removal of low-k dielectric material at greater than about 1000 angstroms per minute. The composition can also be formulated to selectively remove a photoresist layer, leaving the underlying low-k dielectric layer essentially intact.

公开(公告)号：US20090001314A1

公开(公告)日：2009-01-01

申请号：US12146113

申请日：2008-06-25

Applicant: Donald L. Yates

Inventor： Donald L. Yates

IPC: G03F7/42 ,  C09K13/00 ,  C11D7/26

CPC classification number: C09K13/08 ,  B08B3/08 ,  C09K13/00 ,  C09K13/04 ,  C09K13/06 ,  C11D7/08 ,  C11D7/10 ,  C11D7/50 ,  C11D11/0047 ,  C23G1/02 ,  G03F7/423 ,  H01L21/31111 ,  H01L21/31133 ,  Y10S438/948

Abstract: An improved composition and method for cleaning the surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k dielectric material such as silicon dioxide, a photoresist layer overlying a low-k dielectric layer, or both layers from the surface of a wafer. The composition is formulated according to the invention to provide a desired removal rate of the low-k dielectric and/or photoresist from the surface of the wafer. By varying the fluorine ion component, and the amounts of the fluorine ion component and acid, component, and controlling the pH, a composition can be formulated in order to achieve a desired low-k dielectric removal rate that ranges from slow and controlled at about 50 to about 1000 angstroms per minute, to a relatively rapid removal of low-k dielectric material at greater than about 1000 angstroms per minute. The composition can also be formulated to selectively remove a photoresist layer, leaving the underlying low-k dielectric layer essentially intact.

Abstract translation: 提供了用于清洁半导体晶片的表面的改进的组合物和方法。 该组合物可用于选择性地除去低k介电材料，例如二氧化硅，覆盖低k电介质层的光致抗蚀剂层，或从晶片表面两层。 根据本发明配制组合物以从晶片的表面提供低k电介质和/或光致抗蚀剂的期望的去除速率。 通过改变氟离子成分以及氟离子成分和酸，成分和控制pH的量，可以配制组合物以实现期望的低k电介质去除速率，其范围从慢和约在约 每分钟50至约1000埃，以每分钟大约1000埃的速度相对快速地除去低k电介质材料。 组合物也可以配制成选择性地除去光致抗蚀剂层，使底层的低k电介质层基本上完整无缺。

公开(公告)号：US07419768B2

公开(公告)日：2008-09-02

申请号：US10299165

申请日：2002-11-18

Applicant: Donald L. Yates

Inventor： Donald L. Yates

IPC: G03C5/00

CPC classification number: H01L21/02071 ,  H01L21/31133 ,  H01L21/76802 ,  H01L21/76877

Abstract: The invention includes methods of fabricating integrated circuitry and semiconductor processing polymer residue removing solutions. In one implementation, a method of fabricating integrated circuitry includes forming a conductive metal line over a semiconductor substrate. The conductive line is exposed to a solution comprising an inorganic acid, hydrogen peroxide and a carboxylic acid buffering agent. In one implementation, a method of fabricating integrated circuitry includes forming an insulating layer over a semiconductor substrate. A contact opening is at least partially formed into the insulating layer. The contact opening is exposed to a solution comprising an inorganic acid, hydrogen peroxide and a carboxylic acid buffering agent. In one implementation, a semiconductor processing polymer residue removing solution comprises an inorganic acid, hydrogen peroxide and a carboxylic acid buffering agent. Other aspects and implementations are contemplated.

Abstract translation: 本发明包括制造集成电路和半导体处理聚合物残渣除去溶液的方法。 在一个实现中，制造集成电路的方法包括在半导体衬底上形成导电金属线。 导电线暴露于包含无机酸，过氧化氢和羧酸缓冲剂的溶液中。 在一个实施方案中，制造集成电路的方法包括在半导体衬底上形成绝缘层。 接触开口至少部分地形成在绝缘层中。 将接触开口暴露于包含无机酸，过氧化氢和羧酸缓冲剂的溶液中。 在一个实施方案中，半导体加工聚合物残渣除去溶液包含无机酸，过氧化氢和羧酸缓冲剂。 考虑了其他方面和实现。

公开(公告)号：US07312159B2

公开(公告)日：2007-12-25

申请号：US10889201

申请日：2004-07-12

Applicant: Donald L Yates

Inventor： Donald L Yates

IPC: H01L21/302

CPC classification number: C09K13/08 ,  B08B3/08 ,  C09K13/00 ,  C09K13/04 ,  C09K13/06 ,  C11D7/08 ,  C11D7/10 ,  C11D7/50 ,  C11D11/0047 ,  C23G1/02 ,  G03F7/423 ,  H01L21/31111 ,  H01L21/31133 ,  Y10S438/948

Abstract: An improved composition and method for cleaning the surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k dielectric material such as silicon dioxide, a photoresist layer overlying a low-k dielectric layer, or both layers from the surface of a wafer. The composition is formulated according to the invention to provide a desired removal rate of the low-k dielectric and/or photoresist from the surface of the wafer. By varying the fluorine ion component, and the amounts of the fluorine ion component and acid, component, and controlling the pH, a composition can be formulated in order to achieve a desired low-k dielectric removal rate that ranges from slow and controlled at about 50 to about 1000 angstroms per minute, to a relatively rapid removal of low-k dielectric material at greater than about 1000 angstroms per minute. The composition can also be formulated to selectively remove a photoresist layer, leaving the underlying low-k dielectric layer essentially intact.

Abstract translation: 提供了用于清洁半导体晶片的表面的改进的组合物和方法。 该组合物可用于选择性地除去低k介电材料，例如二氧化硅，覆盖低k电介质层的光致抗蚀剂层，或从晶片表面两层。 根据本发明配制组合物以从晶片的表面提供低k电介质和/或光致抗蚀剂的期望的去除速率。 通过改变氟离子成分以及氟离子成分和酸，成分和控制pH的量，可以配制组合物以实现期望的低k电介质去除速率，其范围从慢和约在约 每分钟50至约1000埃，以每分钟大约1000埃的速度相对快速地除去低k电介质材料。 组合物也可以配制成选择性地除去光致抗蚀剂层，使底层的低k电介质层基本上完整无缺。

公开(公告)号：US07163019B2

公开(公告)日：2007-01-16

申请号：US10633069

申请日：2003-08-01

Applicant: Donald L. Yates

Inventor： Donald L. Yates

IPC: B08B3/04

CPC classification number: H01L21/67034 ,  H01L21/02052 ,  H01L21/02057 ,  H01L21/67028 ,  H01L21/67057 ,  Y10S134/902

Abstract: The present invention relates to a method of cleaning and drying a semiconductor structure in a modified conventional gas etch/rinse or dryer vessel. In an embodiment of the present invention, a semiconductor structure is placed into a first treatment vessel and chemically treated. Following the chemical treatment, the semiconductor structure is transferred directly to a second treatment vessel where it is rinsed with DI water and then dried. The second treatment vessel is flooded with both DI water and a gas that is inert to the ambient, such as nitrogen, to form a DI water bath upon which an inert atmosphere is maintained during rinsing. Next, an inert gas carrier laden with IPA vapor is fed into the second treatment vessel. After sufficient time, a layer of IPA has formed upon the surface of the DI water bath to form an IPA-DI water interface. The semiconductor structure is drawn out of the DI water bath at a rate that allows substantially all DI water, and contaminants therein, to be entrained beneath the IPA-DI water interface. In a second embodiment of the present invention, chemical treatment, rinsing, and drying are carried out in a single vessel. In a third embodiment of the present invention, a retrofitted spray/dump rinser with a lid is used for rinsing and drying according to the method of the present invention.

Abstract translation: 本发明涉及一种在改进的常规气体蚀刻/漂洗或干燥容器中清洗和干燥半导体结构的方法。 在本发明的一个实施例中，将半导体结构放置在第一处理容器中并进行化学处理。 化学处理后，将半导体结构直接转移到第二处理容器，在其中用DI水冲洗然后干燥。 第二处理容器充满了DI水和对环境如氮气是惰性的气体，以形成在洗涤期间保持惰性气氛的去离子水浴。 接下来，将载有IPA蒸气的惰性气体载体进料到第二处理容器中。 在足够的时间之后，在去离子水浴表面上形成一层IPA以形成IPA-DI水界面。 将半导体结构从DI水浴中抽出，其速率允许基本上所有的去离子水和其中的污染物被夹带在IPA-DI水界面下面。 在本发明的第二个实施方案中，化学处理，漂洗和干燥在单个容器中进行。 在本发明的第三实施例中，根据本发明的方法，使用具有盖的改装的喷淋/倾卸式冲洗机进行漂洗和干燥。

公开(公告)号：US07087561B2

公开(公告)日：2006-08-08

申请号：US10187163

申请日：2002-07-01

Applicant: Donald L. Yates ,  Max F. Hineman

Inventor： Donald L. Yates ,  Max F. Hineman

IPC: H01L21/302

CPC classification number: C11D7/08 ,  C11D7/265 ,  C11D11/0047

Abstract: A composition for use in semiconductor processing wherein the composition comprises water, phosphoric acid, and an organic acid; wherein the organic acid is ascorbic acid or is an organic acid having two or more carboxylic acid groups (e.g., citric acid). The water can be present in about 40 wt. % to about 85 wt. % of the composition, the phosphoric acid can be present in about 0.01 wt. % to about 10 wt. % of the composition, and the organic acid can be present in about 10 wt. % to about 60 wt. % of the composition. The composition can be used for cleaning various surfaces, such as, for example, patterned metal layers and vias by exposing the surfaces to the composition.

公开(公告)号：US07015529B2

公开(公告)日：2006-03-21

申请号：US10453229

申请日：2003-06-03

Applicant: Donald L. Yates ,  Garry A. Mercaldi

Inventor： Donald L. Yates ,  Garry A. Mercaldi

IPC: H01L29/78

CPC classification number: H01L28/92 ,  G03F7/0035 ,  G03F7/201 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/0275 ,  H01L21/32139 ,  H01L27/10852 ,  H01L28/84 ,  H01L28/91

Abstract: Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical planarization (CMP), thus eliminating CMP-induced defects and variations. The methods utilize localized masking of holes for protection of the inside of the holes during non-mechanical removal of exposed surface layers. The localized masking is accomplished through differential exposure of a resist layer to electromagnetic or thermal energy. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.