公开(公告)号：US06437720B1

公开(公告)日：2002-08-20

申请号：US09785690

申请日：2001-02-16

Applicant: Guangming Yin ,  Bo Zhang

Inventor： Guangming Yin ,  Bo Zhang

IPC: H03M166

CPC classification number: H03M1/0663 ,  H03M1/804

Abstract: A switched-capacitor digital-to-analog converter circuit is disclosed. The switched-capacitor digital-to-analog converter circuit includes crossing switches for each capacitor branch, the crossing switches are used to eliminate cross interference between digital-to-analog converter blocks sharing the same reference voltages.

Abstract translation: 公开了一种开关电容器数模转换器电路。 开关电容器数模转换器电路包括用于每个电容器分支的交叉开关，交叉开关用于消除共享相同参考电压的数模转换器模块之间的交叉干扰。

公开(公告)号：US08750338B2

公开(公告)日：2014-06-10

申请号：US13556863

申请日：2012-07-24

Applicant: Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

Inventor： Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

IPC: H04J3/02

CPC classification number: H04J3/0685 ,  H04J3/04 ,  H04J3/0629 ,  H04L7/0008

Abstract: Provided is a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

Abstract translation: 提供了一种高速比特流数据转换电路，其包括以第一比特率接收第一比特流的输入端口。 数据转换电路接收第一比特流并产生第二比特流，其中第一和第二比特流的数量和比特率不同。 对称路径将来自输入端口的第一比特流传输到数据转换电路，其中它们的传输时间基本相等。 时钟分配电路接收并对称地将时钟信号分配给数据转换电路。 耦合到时钟端口并且位于具有从主干延伸的配对分支的第一对电路路径之间的中央中继线，并且耦合到数据转换电路构成时钟分配电路。 分布式数据时钟信号将数据从第一到第二位流锁存在数据转换电路中。

公开(公告)号：US20120287950A1

公开(公告)日：2012-11-15

申请号：US13556863

申请日：2012-07-24

Applicant: Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

Inventor： Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

IPC: H04J3/02

CPC classification number: H04J3/0685 ,  H04J3/04 ,  H04J3/0629 ,  H04L7/0008

Abstract: Provided is a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

Abstract translation: 提供了一种高速比特流数据转换电路，其包括以第一比特率接收第一比特流的输入端口。 数据转换电路接收第一比特流并产生第二比特流，其中第一和第二比特流的数量和比特率不同。 对称路径将来自输入端口的第一比特流传输到数据转换电路，其中它们的传输时间基本相等。 时钟分配电路接收并对称地将时钟信号分配给数据转换电路。 耦合到时钟端口并且位于具有从主干延伸的配对分支的第一对电路路径之间的中央中继线，并且耦合到数据转换电路构成时钟分配电路。 分布式数据时钟信号将数据从第一到第二位流锁存在数据转换电路中。

公开(公告)号：US07778288B2

公开(公告)日：2010-08-17

申请号：US12014094

申请日：2008-01-15

Applicant: Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

Inventor： Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

IPC: H04J3/02

CPC classification number: H04J3/0685 ,  H04J3/04 ,  H04J3/0629 ,  H04L7/0008

Abstract: Provided is a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

Abstract translation: 提供了一种高速比特流数据转换电路，其包括以第一比特率接收第一比特流的输入端口。 数据转换电路接收第一比特流并产生第二比特流，其中第一和第二比特流的数量和比特率不同。 对称路径将来自输入端口的第一比特流传输到数据转换电路，其中它们的传输时间基本相等。 时钟分配电路接收并对称地将时钟信号分配给数据转换电路。 耦合到时钟端口并且位于具有从主干延伸的配对分支的第一对电路路径之间的中央中继线，并且耦合到数据转换电路构成时钟分配电路。 分布式数据时钟信号将数据从第一到第二位流锁存在数据转换电路中。

公开(公告)号：US07577171B2

公开(公告)日：2009-08-18

申请号：US10361463

申请日：2003-02-10

Applicant: Mohammad Nejad ,  Guangming Yin ,  Ali Ghiasi

Inventor： Mohammad Nejad ,  Guangming Yin ,  Ali Ghiasi

IPC: H04J3/02

CPC classification number: H04L5/023 ,  H04L7/0008

Abstract: A multiple bit stream interface interfaces a first transmit data multiplexing integrated circuit and a second transmit data multiplexing integrated circuit. The multiple bit stream interface includes an interface plurality of transmit bit streams each of which carries a respective bit stream at an interface bit rate. The interface further includes a transmit data clock operating at a frequency corresponding to one-half of the interface bit rate. The first transmit data multiplexing integrated circuit receives a first plurality of transmit bit streams from a communication ASIC at a first bit rate. The second transmit data multiplexing integrated circuit produces a single bit stream output at a line bit rate. The interface plurality of transmit bit streams is divided into a first group and a second group, wherein the first group is carried on first group of lines and the second group is carried on a second group of lines. The transmit data clock is carried on a line that is centered with respect to the first group of lines and the second group of lines such that it resides between the first group of lines and the second group of lines. The interface may also interface a first receive data demultiplexing integrated circuit and a second receive data demultiplexing integrated circuit.

Abstract translation: 多比特流接口将第一发送数据多路复用集成电路和第二发送数据多路复用集成电路接口。 多比特流接口包括多个发送比特流的接口，每个发送比特流以接口比特率携带相应的比特流。 该接口还包括以对应于接口比特率的一半的频率工作的发送数据时钟。 第一发送数据复用集成电路以第一比特率从通信ASIC接收第一多个发送比特流。 第二发送数据复用集成电路以线路比特率产生单个比特流输出。 所述多个发送比特流的接口被分成第一组和第二组，其中所述第一组在第一组线路上承载，并且所述第二组在第二组线路上承载。 发送数据时钟在相对于第一组线路和第二组线路居中的线路上承载，使得它位于第一组线路组与第二组线路组之间。 接口还可以将第一接收数据解复用集成电路和第二接收数据解复用集成电路接口。

公开(公告)号：US07386084B2

公开(公告)日：2008-06-10

申请号：US10456803

申请日：2003-06-06

Applicant: Guangming Yin

Inventor： Guangming Yin

IPC: H04L7/00 ,  H04L25/00 ,  H04L25/40

CPC classification number: H03L7/091 ,  H03K5/135 ,  H04L7/033

Abstract: Aspects of the pattern-independent phase adjustment system includes a single output data XOR gate coupled to a differential input data signal and a bias voltage through a first variable resistor. A single output reference XOR gate may be coupled to a latched differential input signal and the bias voltage through a second variable resistor. At least one latch may be coupled to at least one differential input of the data and reference XOR gate. The single output of the data XOR gate may be a data output of a clock and data recovery circuit (CDR) and the single output of the reference XOR gate may be a reference output of the clock and CDR. No current may flow at the data output of the data XOR gate and the reference output of the reference XOR gate when there are no transitions occurring at an input of the phase detector.

Abstract translation: 独立于图形的相位调整系统的方面包括通过第一可变电阻器耦合到差分输入数据信号和偏置电压的单个输出数据XOR门。 单个输出参考XOR门可以通过第二可变电阻耦合到锁存的差分输入信号和偏置电压。 至少一个锁存器可以耦合到数据和参考XOR门的至少一个差分输入。 数据异或门的单个输出可以是时钟和数据恢复电路（CDR）的数据输出，并且参考异或门的单个输出可以是时钟和CDR的参考输出。 当在相位检测器的输入处没有发生转换时，数据XOR门的数据输出和参考XOR门的参考输出都不会流过电流。

公开(公告)号：US07346082B2

公开(公告)日：2008-03-18

申请号：US10361255

申请日：2003-02-10

Applicant: Ali Ghiasi ,  Mohammad Nejad ,  Guangming Yin

Inventor： Ali Ghiasi ,  Mohammad Nejad ,  Guangming Yin

IPC: H04J3/02

CPC classification number: H04J3/047 ,  H04J3/0685

Abstract: A multiple bit stream interface interfaces a first transmit data multiplexing integrated circuit and a second transmit data multiplexing integrated circuit. The multiple bit stream interface includes an interface plurality of transmit bit streams each of which carries a respective bit stream at an interface bit rate and in a natural order. The interface further includes a transmit data clock operating at a frequency corresponding to one-half of the interface bit rate. The first transmit data multiplexing integrated circuit receives a first plurality of transmit bit streams from a communication ASIC at a first bit rate. The second transmit data multiplexing integrated circuit produces a single bit stream output at a line bit rate. The interface plurality of transmit bit streams is divided into a first group and a second group, wherein the first group is carried on first group of lines and the second group is carried on a second group of lines. The transmit data clock is carried on a line that is centered with respect to the first group of lines and the second group of lines such that it resides between the first group of lines and the second group of lines. The interface may also interface a first receive data demultiplexing integrated circuit and a second receive data demultiplexing integrated circuit.

Abstract translation: 多比特流接口将第一发送数据多路复用集成电路和第二发送数据多路复用集成电路接口。 多比特流接口包括多个发送比特流的接口，每个发送比特流以接口比特率和自然顺序携带相应的比特流。 该接口还包括以对应于接口比特率的一半的频率工作的发送数据时钟。 第一发送数据复用集成电路以第一比特率从通信ASIC接收第一多个发送比特流。 第二发送数据复用集成电路以线路比特率产生单个比特流输出。 所述多个发送比特流的接口被分成第一组和第二组，其中所述第一组在第一组线路上承载，并且所述第二组在第二组线路上承载。 发送数据时钟在相对于第一组线路和第二组线路居中的线路上承载，使得它位于第一组线路组和第二组线路组之间。 接口还可以将第一接收数据解复用集成电路和第二接收数据解复用集成电路接口。

公开(公告)号：US20050248396A1

公开(公告)日：2005-11-10

申请号：US10841766

申请日：2004-05-07

Applicant: Mario Caresosa ,  Afshin Momtaz ,  Guangming Yin

Inventor： Mario Caresosa ,  Afshin Momtaz ,  Guangming Yin

IPC: H03F3/45 ,  H03G1/00

CPC classification number: H03G1/007 ,  H03F3/45188 ,  H03F3/45197 ,  H03F2203/45504 ,  H03F2203/45638 ,  H03G1/0029 ,  H03G1/0088

Abstract: An input processing circuit includes a first and second input transistors for receiving a differential pair of first and second input signals, respectively. At least one resistor is coupled between first terminals of the first and second input transistors. The input processing circuit includes a variable gain amplifier (VGA) circuit. At least one first transistor has a gate terminal, and is coupled between the first terminals of the first and second input transistors. At least one second transistor has a gate terminal, and is coupled between the first terminals of the first and second input transistors. A gate switch is coupled to the gate terminal of the at least one second transistor. The at least one first transistor and the at least one second transistor adjust a gain of the input processing circuit in response to a control voltage. The control voltage is applied to the gate terminal of the at least one first transistor, and the control voltage is applied to the gate terminal of the at least one second transistor through the gate switch.

Abstract translation: 输入处理电路包括分别用于接收第一和第二输入信号的差分对的第一和第二输入晶体管。 至少一个电阻耦合在第一和第二输入晶体管的第一端之间。 输入处理电路包括可变增益放大器（VGA）电路。 至少一个第一晶体管具有栅极端子，并且耦合在第一和第二输入晶体管的第一端子之间。 至少一个第二晶体管具有栅极端子，并且耦合在第一和第二输入晶体管的第一端子之间。 栅极开关耦合到至少一个第二晶体管的栅极端子。 所述至少一个第一晶体管和所述至少一个第二晶体管响应于控制电压调整所述输入处理电路的增益。 控制电压被施加到至少一个第一晶体管的栅极端子，并且通过栅极开关将控制电压施加到至少一个第二晶体管的栅极端子。

公开(公告)号：US20050218984A1

公开(公告)日：2005-10-06

申请号：US11133723

申请日：2005-05-20

Applicant: Guangming Yin

Inventor： Guangming Yin

IPC: H03D13/00 ,  H03F3/45 ,  H03K19/21 ,  H04L7/033

CPC classification number: H03D13/003 ,  H03K19/215 ,  H04L7/033

Abstract: Aspects of the invention provide a fast one level zero-current-state XOR gate. An embodiment of the invention provides a first pair of differentially configured transistors and a level shifting resistor coupled to the first pair of differentially configured transistors. The one level zero-current-state XOR gate may also include a second pair of differentially configured transistors. A core of the XOR gate may be coupled to outputs of the first and the second pairs of differentially configured transistors.

Abstract translation: 本发明的方面提供了快速的一级零电流状态异或门。 本发明的实施例提供了第一对差分配置的晶体管和耦合到第一对差分配置的晶体管的电平转换电阻器。 一级零电流状态XOR门还可以包括第二对差分配置的晶体管。 XOR门的核可以耦合到第一对和第二对差分配置的晶体管的输出。

公开(公告)号：US06909332B2

公开(公告)日：2005-06-21

申请号：US10639079

申请日：2003-08-12

Applicant: Guangming Yin ,  Bo Zhang ,  Ichiro Fujimori

Inventor： Guangming Yin ,  Bo Zhang ,  Ichiro Fujimori

IPC: H03B5/12 ,  H03L7/099 ,  H03L7/10 ,  H04J3/04 ,  H04J3/06 ,  H04L7/00 ,  H03L7/00

CPC classification number: H03L7/10 ,  H03B5/1209 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/124 ,  H03B5/1265 ,  H03L7/099 ,  H04J3/04 ,  H04J3/0629 ,  H04L7/0008

Abstract: The present invention provides a method for tuning output drivers to an operating frequency based on settings used to tune other devices within the device such as a VCO. First the VCO within a PLL and clock circuit is tuned to the desired operating frequency. This operating frequency then corresponds to a discrete tuning setting. The discrete setting that causes the VCO to function at the operating frequency are then transferred to scaled amplifiers within output drivers. These drivers are then tuned to the operating frequency with these settings. This process eliminates the need to individually tune each output driver to function properly at the operating frequency.