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    COMPILER ASSISTED LOW POWER AND HIGH PERFORMANCE LOAD HANDLING
    36.
    发明申请
    COMPILER ASSISTED LOW POWER AND HIGH PERFORMANCE LOAD HANDLING 有权
    编译器辅助低功耗和高性能负载处理

    公开(公告)号：US20110161632A1

    公开(公告)日：2011-06-30

    申请号：US11967230

    申请日：2007-12-30

    Applicant: Tingting Sha ,  Chris Wilkerson ,  Herbert Hum ,  Alaa R. Alameldeen

    Inventor： Tingting Sha ,  Chris Wilkerson ,  Herbert Hum ,  Alaa R. Alameldeen

    IPC: G06F9/30

    CPC classification number: G06F9/30043 ,  G06F8/41 ,  G06F8/4442 ,  G06F9/30047 ,  G06F9/30185 ,  G06F9/3826 ,  G06F9/3891

    Abstract: A method and apparatus for handling low power and high performance loads is herein described. Software, such as a compiler, is utilized to identify producer loads, consumer reuse loads, and consumer forwarded loads. Based on the identification by software, hardware is able to direct performance of the load directly to a load value buffer, a store buffer, or a data cache. As a result, accesses to cache are reduced, through direct loading from load and store buffers, without sacrificing load performance.

    Abstract translation: 这里描述了用于处理低功率和高性能负载的方法和装置。 使用诸如编译器的软件来识别生产者负载，消费者重用负载和消费者转发的负载。 基于软件识别，硬件能够将负载的性能直接引导到负载值缓冲器，存储缓冲器或数据高速缓存。 因此，通过从加载和存储缓冲区直接加载，可以减少对高速缓存的访问，而不会牺牲负载性能。

    High speed DRAM cache architecture
    37.
    发明授权
    High speed DRAM cache architecture 有权
    高速DRAM缓存架构

    公开(公告)号：US07350016B2

    公开(公告)日：2008-03-25

    申请号：US11329994

    申请日：2006-01-10

    Applicant: Kuljit S. Bains ,  Herbert Hum ,  John Halbert

    Inventor： Kuljit S. Bains ,  Herbert Hum ,  John Halbert

    IPC: G06F12/08

    CPC classification number: G06F12/0893 ,  G06F12/0864 ,  G06F12/0882

    Abstract: A high speed DRAM cache architecture. One disclosed embodiment includes a multiplexed bus interface to interface with a multiplexed bus. A cache control circuit drives a row address portion of an address on the multiplexed bus interface and a command to open a memory page containing data for a plurality of ways. The cache control circuit subsequently drives a column address including at least a way indicator to the multiplexed bus interface.

    Abstract translation: 高速DRAM缓存架构。 一个公开的实施例包括与多路复用总线接口的多路复用总线接口。 高速缓存控制电路驱动复用总线接口上的地址的行地址部分，以及打开包含多路数据的存储器页的命令。 高速缓存控制电路随后将包括至少一路指示符的列地址驱动到多路复用的总线接口。

    High speed DRAM cache architecture
    39.
    发明授权
    High speed DRAM cache architecture 有权
    高速DRAM缓存架构

    公开(公告)号：US07054999B2

    公开(公告)日：2006-05-30

    申请号：US10210908

    申请日：2002-08-02

    Applicant: Kuljit S. Bains ,  Herbert Hum ,  John Halbert

    Inventor： Kuljit S. Bains ,  Herbert Hum ,  John Halbert

    IPC: G06F12/08

    CPC classification number: G06F12/0893 ,  G06F12/0864 ,  G06F12/0882

    Abstract: A high speed DRAM cache architecture. One disclosed embodiment includes a multiplexed bus interface to interface with a multiplexed bus. A cache control circuit drives a row address portion of an address on the multiplexed bus interface and a command to open a memory page containing data for a plurality of ways. The cache control circuit subsequently drives a column address including at least a way indicator to the multiplexed bus interface.

    Abstract translation: 高速DRAM缓存架构。 一个公开的实施例包括与多路复用总线接口的多路复用总线接口。 高速缓存控制电路驱动复用总线接口上的地址的行地址部分，以及打开包含多路数据的存储器页的命令。 高速缓存控制电路随后将包括至少一路指示符的列地址驱动到多路复用总线接口。

    Multi-node chipset lock flow with peer-to-peer non-posted I/O requests
    40.
    发明申请
    Multi-node chipset lock flow with peer-to-peer non-posted I/O requests 有权
    具有点对点非贴片I / O请求的多节点芯片组锁定流

    公开(公告)号：US20050273400A1

    公开(公告)日：2005-12-08

    申请号：US10859891

    申请日：2004-06-02

    Applicant: Robert Blankenship ,  Robert Greiner ,  Herbert Hum ,  Kenneth Creta ,  Buderya Acharya

    Inventor： Robert Blankenship ,  Robert Greiner ,  Herbert Hum ,  Kenneth Creta ,  Buderya Acharya

    IPC: G06F17/60

    CPC classification number: G06F13/387 ,  G06Q10/087

    Abstract: Systems and methods of managing transactions provide for receiving a first flush command at a first I/O hub, wherein the first flush command is dedicated to non-posted transactions. One embodiment further provides for halting an inbound ordering queue of the first I/O hub with regard to non-posted transactions in response to the first flush command and flushing a non-posted transaction from an outgoing buffer of the first I/O hub to a second I/O hub while the inbound ordering queue is halted with regard to non-posted transactions.

    Abstract translation: 管理事务的系统和方法提供在第一I / O集线器处接收第一冲洗命令，其中第一冲洗命令专用于未发布的事务。 一个实施例进一步提供响应于第一冲洗命令而停止关于非发布的事务的第一I / O集线器的入站订购队列，并将未发布的事务从第一I / O集线器的输出缓冲器刷新到 第二个I / O中枢，而对于未发布的事务，入站订购队列被停止。

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