公开(公告)号：US20130070546A1

公开(公告)日：2013-03-21

申请号：US13423759

申请日：2012-03-19

Applicant: Osamu Nagao ,  Hitoshi Shiga

Inventor： Osamu Nagao ,  Hitoshi Shiga

IPC: G11C29/44

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C29/04 ,  G11C29/82 ,  G11C2029/4402

Abstract: A nonvolatile semiconductor memory device according to the embodiment comprises a memory cell array including plural blocks arranged in a first direction, each block containing plural memory cells operative to store data; a row decoder including a faulty block information holder circuit operative to store faulty block information indicative that the block is a faulty block; and a faulty block detector circuit operative to, when each of block groups includes at least one of the plural blocks, subject one of the block groups to a first detection step of simultaneously and intensively referring to pieces of faulty block information respectively corresponding to the plural blocks in one of the block groups simultaneously to detect whether the block group contains a faulty block.

Abstract translation: 根据实施例的非易失性半导体存储器件包括：存储单元阵列，包括沿第一方向布置的多个块，每个块包含可操作以存储数据的多个存储单元; 行解码器，其包括故障块信息保持器电路，用于存储指示所述块是故障块的故障块信息; 以及故障块检测器电路，其操作用于当每个块组包括所述多个块中的至少一个时，将所述块组中的一个对象到第一检测步骤，同时且集中地参考分别对应于所述多个块的故障块信息 块中的块之一同时检测块组是否包含故障块。

公开(公告)号：US08205039B2

公开(公告)日：2012-06-19

申请号：US12725519

申请日：2010-03-17

Applicant: Osamu Nagao ,  Hitoshi Shiga

Inventor： Osamu Nagao ,  Hitoshi Shiga

IPC: G06F12/00

CPC classification number: G06F12/0246 ,  G06F2212/7209

Abstract: A nonvolatile semiconductor memory device according to one aspect of the present invention includes: a memory cell array provided to perform programming in page units; and a control circuit provided to control the programming. The control circuit includes: means that performs a first detection for memory cells in a part provided as a unit smaller than a page, concurrently with programming to memory cells to be written in a page; and means that subjects the memory cells in the page to a second detection that takes into consideration a failure relief due to a redundant region, when the number of memory cells of unwritten state in the part as detected by the first detection becomes equal to or less than a first constant, and that ends the program operation when the number of memory cells of unwritten state in the page becomes equal to or less than a second constant.

Abstract translation: 根据本发明的一个方面的非易失性半导体存储器件包括：设置为以页为单位执行编程的存储单元阵列; 以及设置用于控制编程的控制电路。 控制电路包括：对存储单元进行第一检测的装置，该存储单元在作为小于页面的单位提供的部分中，同时对要写入页面的存储单元进行编程; 并且意味着当第一检测中检测到的部分中未写入状态的存储单元的数目等于或等于或等于或小于第二检测时，考虑到冗余区域引起的故障缓解， 并且当页面中未写入状态的存储单元的数量等于或小于第二常数时，结束程序操作。

公开(公告)号：US20120063234A1

公开(公告)日：2012-03-15

申请号：US13226180

申请日：2011-09-06

Applicant: Hitoshi SHIGA ,  Masahiro Yoshihara

Inventor： Hitoshi SHIGA ,  Masahiro Yoshihara

IPC: G11C16/10 ,  G11C16/06 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C16/30

Abstract: According to one embodiment, a memory system includes a first nonvolatile semiconductor memory, a second nonvolatile semiconductor memory and a controller. The first memory has memory cells and executes a first operation that is at least one of write, read, and erase operations with respect to the memory cells. The first operation includes a first sub-operation and a second-sub operation that consume a current which is equal to or higher than a predetermined current. The second memory has memory cells and executes a second operation that is at least one of write, read, and erase operations with respect to the memory cells. The second operation includes a third sub-operation and a fourth sub-operation that consume a current which is equal to or higher than the predetermined current. The controller controls the first operation and the second operation of the first memory and the second memory.

Abstract translation: 根据一个实施例，存储器系统包括第一非易失性半导体存储器，第二非易失性半导体存储器和控制器。 第一存储器具有存储器单元并且执行与存储器单元相关的写入，读取和擦除操作中的至少一个的第一操作。 第一操作包括消耗等于或高于预定电流的电流的第一子操作和第二子操作。 第二存储器具有存储单元并且执行与存储单元相关的写入，读取和擦除操作中的至少一个的第二操作。 第二操作包括消耗等于或高于预定电流的电流的第三子操作和第四子操作。 控制器控制第一存储器和第二存储器的第一操作和第二操作。

公开(公告)号：US20110228615A1

公开(公告)日：2011-09-22

申请号：US13033259

申请日：2011-02-23

Applicant: Hitoshi SHIGA

Inventor： Hitoshi SHIGA

IPC: G11C7/10

CPC classification number: G11C7/1006 ,  G11C29/846

Abstract: According to one embodiment, a semiconductor memory device includes unit structures. Each unit structure includes bit lines, memory cells, sense amplifiers, a first data line, a computing circuit, a second data line, and data latches. The bit lines are connected to memory cells. The sense amplifiers are connected to respective bit lines adjacent to each other. The first data line is commonly connected to the sense amplifiers. The computing circuit is connected to the first data line. The second data line is connected to the computing circuit. The data latches are connected to the second data line. The unit structures are independent from one another. At least one of the unit structures is a spare unit structure. One of the unit structures is configured to be replaceable with the spare unit structure.

Abstract translation: 根据一个实施例，半导体存储器件包括单元结构。 每个单元结构包括位线，存储单元，读出放大器，第一数据线，计算电路，第二数据线和数据锁存器。 位线连接到存储单元。 读出放大器连接到彼此相邻的相应位线。 第一条数据线通常连接到读出放大器。 计算电路连接到第一数据线。 第二数据线连接到计算电路。 数据锁存器连接到第二条数据线。 单位结构彼此独立。 至少一个单元结构是备用单元结构。 其中一个单元结构被配置为可替换备用单元结构。

公开(公告)号：US07859910B2

公开(公告)日：2010-12-28

申请号：US12333656

申请日：2008-12-12

Applicant: Hitoshi Shiga

Inventor： Hitoshi Shiga

IPC: G11C16/04

CPC classification number: G11C8/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/3454 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array including a plurality of word lines; a parameter storage part which stores a parameter related to a programming voltage which is applied to a word line for programming data; a word line selection circuit which selects a word line among the plurality of word lines which is connected to a memory cell to be programmed with data; a voltage application circuit which applies a programming voltage to the selected word line according to the parameter; a verify circuit which performs verification of programmed data; a control part which outputs a signal for selecting a word line and repeats the operations of the voltage application circuit until the verification is successful; a calculation circuit which calculates an average value of the number of times the control part repeats the operations of the voltage application circuit per each word line; and a parameter setting circuit which sets the parameter using the average value calculated.

Abstract translation: 根据本发明的一个实施例的非易失性半导体存储器件包括：包括多个字线的存储单元阵列; 参数存储部，其存储与应用于用于编程数据的字线的编程电压相关的参数; 字线选择电路，其选择连接到要被数据编程的存储单元的多个字线中的字线; 电压施加电路，其根据所述参数对所选择的字线施加编程电压; 执行编程数据验证的验证电路; 控制部，其输出用于选择字线的信号，并重复所述电压施加电路的动作，直到所述验证成功为止; 计算电路，其计算控制部分重复每个字线的电压施加电路的操作次数的平均值; 以及使用所计算的平均值来设定参数的参数设定电路。

公开(公告)号：US07826268B2

公开(公告)日：2010-11-02

申请号：US12236015

申请日：2008-09-23

Applicant: Norihiro Fujita ,  Toshihiko Himeno ,  Hitoshi Shiga

Inventor： Norihiro Fujita ,  Toshihiko Himeno ,  Hitoshi Shiga

IPC: G11C11/34 ,  G11C16/04

CPC classification number: G11C5/147 ,  G11C16/0483 ,  G11C29/02 ,  G11C29/025

Abstract: A nonvolatile semiconductor memory, has a first wire; a second wire adjacent to the first wire; a third wire disposed next to the second wire such that the second wire is disposed between the first wire and the third wire; a power supply circuit for setting each of the wires at a predetermined potential; and a determining circuit for determining presence or absence of a short circuit between the wires.

Abstract translation: 非易失性半导体存储器，具有第一线; 邻近第一线的第二线; 设置在所述第二导线旁边的第三线，使得所述第二线布置在所述第一线和所述第三线之间; 电源电路，用于将每个电线设置在预定电位; 以及确定电线之间短路存在或不存在的确定电路。

公开(公告)号：US20100080056A1

公开(公告)日：2010-04-01

申请号：US12557898

申请日：2009-09-11

Applicant: Hitoshi SHIGA

Inventor： Hitoshi SHIGA

IPC: G11C16/04 ,  G11C16/06 ,  H01L29/788

CPC classification number: G11C16/10 ,  G06F11/1072 ,  G11C11/5628 ,  G11C16/0483 ,  G11C29/00 ,  G11C2211/5641 ,  H01L27/11521

Abstract: A semiconductor memory system includes: a memory cell array having a plurality of memory cells arranged therein, the plurality of memory cells capable of storing N bits of information in each memory cell (where N is a natural number more than 3, other than a power of two); a control circuit configured to control read, write, and erase operations on the memory cell array; and an ECC circuit configured to correct data read from the memory cell array, based on redundant data. The memory cells that share one of word lines and can be written or read at a time are configured to store multiple pages of data therein. A total amount of data stored in the multiple pages is set to a power-of-two number of bits, and the redundant data is stored in a residual portion of the multiple pages.

Abstract translation: 半导体存储器系统包括：存储单元阵列，其中布置有多个存储器单元，所述多个存储单元能够在每个存储单元中存储N位信息（其中N是大于3的自然数，除了功率 的两个）; 控制电路，被配置为控制对所述存储单元阵列的读，写和擦除操作; 以及ECC电路，被配置为基于冗余数据校正从存储单元阵列读取的数据。 共享字线之一并且可以一次写入或读取的存储单元被配置为在其中存储多页数据。 存储在多页中的数据的总量被设置为两位数，并且冗余数据被存储在多页的剩余部分中。

公开(公告)号：US20090154244A1

公开(公告)日：2009-06-18

申请号：US12333656

申请日：2008-12-12

Applicant: Hitoshi SHIGA

Inventor： Hitoshi SHIGA

IPC: G11C16/04 ,  G11C16/06 ,  G11C8/00

CPC classification number: G11C8/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/3454 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array including a plurality of word lines; a parameter storage part which stores a parameter related to a programming voltage which is applied to a word line for programming data; a word line selection circuit which selects a word line among the plurality of word lines which is connected to a memory cell to be programmed with data; a voltage application circuit which applies a programming voltage to the selected word line according to the parameter; a verify circuit which performs verification of programmed data; a control part which outputs a signal for selecting a word line and repeats the operations of the voltage application circuit until the verification is successful; a calculation circuit which calculates an average value of the number of times the control part repeats the operations of the voltage application circuit per each word line; and a parameter setting circuit which sets the parameter using the average value calculated.

Abstract translation: 根据本发明的一个实施例的非易失性半导体存储器件包括：包括多个字线的存储单元阵列; 参数存储部，其存储与应用于用于编程数据的字线的编程电压相关的参数; 字线选择电路，其选择连接到要被数据编程的存储单元的多个字线中的字线; 电压施加电路，其根据所述参数对所选择的字线施加编程电压; 执行编程数据验证的验证电路; 控制部，其输出用于选择字线的信号，并重复所述电压施加电路的动作，直到所述验证成功为止; 计算电路，其计算控制部分重复每个字线的电压施加电路的操作次数的平均值; 以及使用所计算的平均值来设定参数的参数设定电路。

公开(公告)号：US20090080261A1

公开(公告)日：2009-03-26

申请号：US12236015

申请日：2008-09-23

Applicant: Norihiro Fujita ,  Toshihiko Himeno ,  Hitoshi Shiga

Inventor： Norihiro Fujita ,  Toshihiko Himeno ,  Hitoshi Shiga

IPC: G11C16/06 ,  G11C5/14

CPC classification number: G11C5/147 ,  G11C16/0483 ,  G11C29/02 ,  G11C29/025

Abstract: A nonvolatile semiconductor memory, has a first wire; a second wire adjacent to the first wire; a third wire disposed next to the second wire such that the second wire is disposed between the first wire and the third wire; a power supply circuit for setting each of the wires at a predetermined potential; and a determining circuit for determining presence or absence of a short circuit between the wires.

Abstract translation: 非易失性半导体存储器，具有第一线; 邻近第一线的第二线; 设置在所述第二导线旁边的第三线，使得所述第二线布置在所述第一线和所述第三线之间; 电源电路，用于将每个电线设置在预定电位; 以及确定电线之间短路存在或不存在的确定电路。

公开(公告)号：US07369454B2

公开(公告)日：2008-05-06

申请号：US11193462

申请日：2005-08-01

Applicant: Hitoshi Shiga

Inventor： Hitoshi Shiga

IPC: G11C8/00

CPC classification number: G11C8/12 ,  G11C16/0483 ,  G11C16/08

Abstract: A semiconductor integrated circuit device comprises several blocks including a word line connected with a memory cell, a row decoder selecting the word line, and a block decoder selecting the block. The block decoder includes a logical address register holding logical block address corresponding to the several blocks and a block status register holding a block status. The block decoder selects a block in which input block address and input block status match with held logical block address and held block status, respectively.

Abstract translation: 半导体集成电路器件包括若干块，包括与存储单元连接的字线，选择字线的行解码器和选择该块的块解码器。 块解码器包括保存对应于几个块的逻辑块地址的逻辑地址寄存器和保持块状态的块状态寄存器。 块解码器分别选择输入块地址和输入块状态与保持的逻辑块地址匹配并保持块状态的块。