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    SM3 HASH ALGORITHM ACCELERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
    31.
    发明申请
    SM3 HASH ALGORITHM ACCELERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 有权

    公开(公告)号：US20250088348A1

    公开(公告)日：2025-03-13

    申请号：US18889148

    申请日：2024-09-18

    Applicant: Intel Corporation

    Inventor： Shay GUERON ,  Vlad KRASNOV

    IPC: H04L9/06 ,  G06F9/30 ,  G06F9/38 ,  G06F21/72 ,  G09C1/00

    Abstract: A processor includes a decode unit to decode an SM3 two round state word update instruction. The instruction is to indicate one or more source packed data operands. The source packed data operand(s) are to have eight 32-bit state words Aj, Bj, Cj, Dj, Ej, Fj, Gj, and Hj that are to correspond to a round (j) of an SM3 hash algorithm. The source packed data operand(s) are also to have a set of messages sufficient to evaluate two rounds of the SM3 hash algorithm. An execution unit coupled with the decode unit is operable, in response to the instruction, to store one or more result packed data operands, in one or more destination storage locations. The result packed data operand(s) are to have at least four two-round updated 32-bit state words Aj+2, Bj+2, Ej+2, and Fj+2, which are to correspond to a round (j+2) of the SM3 hash algorithm.

    LATERAL ETCHING PROCESS TO REMOVE METAL GATE FOOT STRUCTURES
    33.
    发明申请
    LATERAL ETCHING PROCESS TO REMOVE METAL GATE FOOT STRUCTURES 有权

    公开(公告)号：US20250087530A1

    公开(公告)日：2025-03-13

    申请号：US18463436

    申请日：2023-09-08

    Applicant: Intel Corporation

    Inventor： Chiao-Ti Huang ,  Tao Chu ,  Guowei Xu ,  Robin Chao ,  Feng Zhang ,  Yang Zhang ,  Ting-Hsiang Hung ,  Anand Murthy

    IPC: H01L21/762 ,  H01L21/768 ,  H01L23/48 ,  H01L27/088 ,  H01L27/12

    Abstract: Techniques are provided to form semiconductor devices where portions of the gate structure (e.g., foot structures) adjacent to the subfins have been removed. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure includes a gate dielectric and a gate electrode. The gate structure may be interrupted, for example, between two transistors with a gate cut that extends through an entire thickness of the gate structure and includes dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. The gate cut includes dielectric lobe structures that extend outwards from the sidewalls of the gate cut. The lobe structures effectively replace foot structures of the gate structure between the gate cut and subfin portions of the semiconductor fins. Removing the gate foot structures contributes to the reduction of the parasitic capacitance in the semiconductor device.

    UNBLOCKING THE INTEGER PIPELINE DURING MATH PIPELINE PHASES IN A GRAPHICS ENVIRONMENT
    34.
    发明申请
    UNBLOCKING THE INTEGER PIPELINE DURING MATH PIPELINE PHASES IN A GRAPHICS ENVIRONMENT 有权

    公开(公告)号：US20250085969A1

    公开(公告)日：2025-03-13

    申请号：US18462832

    申请日：2023-09-07

    Applicant: Intel Corporation

    Inventor： Shuai Mu ,  Supratim Pal ,  Pradeep Golconda ,  Srilakshmi Jammula ,  Jiasheng Chen

    IPC: G06F9/30 ,  G06F9/38

    Abstract: An apparatus to facilitate unblocking the integer pipeline during math pipeline phases in a graphics environment is disclosed. The apparatus includes an execution resource comprising: a thread arbiter; a plurality of execution pipeline hardware circuitry comprising a math execution pipeline and an integer execution pipeline to share resources of the thread arbiter; arbitration hardware circuitry to determine whether the math execution pipeline is available for loading math operand data of a math instruction; and a math instruction staging buffer to store the math operand data responsive to the math execution pipeline not being available; wherein the integer execution pipeline is to receive integer operand data for an integer instruction while bypassing the math operand data in the math instruction staging buffer; and wherein the math execution pipeline is to receive, responsive to the math execution pipeline becoming available, the math operand data from the math instruction staging buffer.

    Radiation shield with zipper
    36.
    发明授权
    Radiation shield with zipper 有权

    公开(公告)号：US12250800B2

    公开(公告)日：2025-03-11

    申请号：US17482244

    申请日：2021-09-22

    Applicant: Intel Corporation

    Inventor： Yew San Lim ,  Jeff Ku ,  Boon Ping Koh ,  Min Suet Lim ,  Tin Poay Chuah

    IPC: H05K9/00 ,  H05K1/02 ,  H05K7/20

    Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a radiation shield that includes a zipper. The radiation shield can include a wall that extends from a support structure of the electronic device, a first portion that is coupled to a cold plate over a radiation source, a second portion that is coupled to the wall, and a zipper that can zip the first portion to the second portion together and can unzip to separate the first portion from the second portion.

    Phase locked loop assisted fast start-up apparatus and method
    38.
    发明授权
    Phase locked loop assisted fast start-up apparatus and method 有权

    公开(公告)号：US12249997B2

    公开(公告)日：2025-03-11

    申请号：US17338497

    申请日：2021-06-03

    Applicant: Intel Corporation

    Inventor： Somnath Kundu ,  Hao Luo ,  Brent Carlton

    IPC: H03L7/099

    Abstract: An apparatus and method are provided to re-configure an existing low-jitter phase locked loop (PLL) circuit for fast start-up during system wake-up. During system start-up, a feed-back path of the PLL is disconnected to independently control the VCO frequency. This independently controlled VCO then injects energy into a resonator (e.g., a crustal oscillator) for its fast start-up. Once a resonance frequency of the resonator is detected and an oscillation builds up in the resonator, a VCO control voltage is stored. The PLL feedback is then restored and the stored VCO control voltage is applied to perform phase-locking operation. Since the PLL control voltage is already set to the desired operating point, the PLL lock time is very small.

    Virtualization of interprocessor interrupts
    40.
    发明授权
    Virtualization of interprocessor interrupts 有权

    公开(公告)号：US12248800B2

    公开(公告)日：2025-03-11

    申请号：US17561433

    申请日：2021-12-23

    Applicant: Intel Corporation

    Inventor： Gilbert Neiger ,  Rajesh Sankaran ,  Hisham Shafi

    IPC: G06F9/455 ,  G06F13/24

    Abstract: Embodiments of apparatuses, methods, and systems for virtualization of interprocessor interrupts are disclosed. In an embodiment, an apparatus includes a plurality of processor cores; an interrupt controller register; and logic to, in response to a write from a virtual machine to the interrupt controller register, record an interprocessor interrupt in a first data structure configured by a virtual machine monitor and send a notification of the interprocessor interrupt to at least one of the plurality of processor cores.

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