公开(公告)号：US08008177B2

公开(公告)日：2011-08-30

申请号：US10621292

申请日：2003-07-17

Applicant: Min-chul San ,  Ja-hum Ku ,  Chul-sung Kim ,  Kwan-jong Roh ,  Min-joo Kim

Inventor： Min-chul San ,  Ja-hum Ku ,  Chul-sung Kim ,  Kwan-jong Roh ,  Min-joo Kim

IPC: H01L21/28

CPC classification number: H01L29/6653 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/78

Abstract: A method for fabricating a semiconductor device is provided using a nickel salicide process. The method includes forming a gate pattern and a source/drain region on a silicon substrate, forming a Ni-based metal layer for silicide on the silicon substrate where the gate pattern and the source/drain region are formed, and forming an N-rich titanium nitride layer on the Ni-based metal layer for silicide. Next, a thermal treatment is applied to the silicon substrate where the Ni-based metal layer for silicide and the N-rich titanium nitride layer are formed, thereby forming a nickel silicide on each of the gate pattern and the source/drain region. Then, the Ni-based metal layer for silicide and the N-rich titanium nitride layer are selectively removed to expose a top portion of a nickel silicide layer formed on the gate pattern and the source/drain region. Thus, as the N-rich titanium nitride layer is formed on the Ni-based metal layer for silicide, a silicide residue is prevented from forming a spacer and a field region formed of a field oxide layer.

Abstract translation: 使用镍硅化物工艺提供半导体器件的制造方法。 该方法包括在硅衬底上形成栅极图案和源极/漏极区域，在形成栅极图案和源极/漏极区域的硅衬底上形成用于硅化物的Ni基金属层，并形成富N 用于硅化物的Ni基金属层上的氮化钛层。 接下来，对形成硅化物的Ni基金属层和形成有N的氮化钛层的硅基板进行热处理，从而在栅极图案和源极/漏极区域的每一个上形成硅化镍。 然后，选择性地除去用于硅化物的Ni基金属层和富N极氮化钛层，以暴露形成在栅极图案和源极/漏极区上的硅化镍层的顶部。 因此，由于在用于硅化物的Ni基金属层上形成富N的氮化钛层，因此防止了硅化物残留物形成间隔物和由场氧化物层形成的场区。

公开(公告)号：US07781322B2

公开(公告)日：2010-08-24

申请号：US10726638

申请日：2003-12-04

Applicant: Ja-Hum Ku ,  Kwan-Jong Roh ,  Min-Chul Sun ,  Min-Joo Kim

Inventor： Ja-Hum Ku ,  Kwan-Jong Roh ,  Min-Chul Sun ,  Min-Joo Kim

IPC: H01L21/3205

CPC classification number: H01L29/665 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/28518 ,  H01L29/4941 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: Provided are exemplary methods for forming a nickel silicide layer and semiconductor devices incorporating a nickel silicide layer that provides increased stability for subsequent processing at temperatures above 450° C. In particular, the nickel silicide layer is formed from a nickel alloy having a minor portion of an alloying metal, such as tantalum, and exhibits reduced agglomeration and retarded the phase transition between NiSi and NiSi2 to suppress increases in the sheet resistance and improve the utility for use with fine patterns. As formed, the nickel silicide layer includes both a lower layer consisting primarily of nickel and silicon and a thinner upper layer that incorporates the majority of the alloying metal.

Abstract translation: 提供了用于形成硅化镍层的示例性方法和结合有硅化镍层的半导体器件，其为在450℃以上的温度下进行后续处理提供了更高的稳定性。特别地，硅化镍层由具有少部分 合金化金属如钽，并且显示减少的结块并延缓NiSi和NiSi2之间的相变，以抑制薄层电阻的增加并提高使用精细图案的效用。 如所形成的那样，硅化镍层包括主要由镍和硅组成的下层和掺入大部分合金金属的较薄的上层。

公开(公告)号：US07586175B2

公开(公告)日：2009-09-08

申请号：US11551864

申请日：2006-10-23

Applicant: Kyoung Woo Lee ,  Ja Hum Ku ,  Ki Chul Park ,  Seung Man Choi

Inventor： Kyoung Woo Lee ,  Ja Hum Ku ,  Ki Chul Park ,  Seung Man Choi

IPC: H01L23/544 ,  H01L21/4763

CPC classification number: H01L23/53238 ,  H01L21/2885 ,  H01L23/564 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor wafer having multi-layer metallization structures that are fabricated to include embedded interconnection structures which serve as low-resistance electroplating current paths to conduct bulk electroplating current fed to portions of a metallic seed layer at peripheral surface regions of the wafer to portions of the metallic seed layer at inner/central surface regions of the semiconductor wafer to achieve uniformity in metal plating in chip regions across the wafer.

Abstract translation: 具有多层金属化结构的半导体晶片，其被制造为包括用作低电阻电镀电流路径的嵌入式互连结构，以将在晶片的外围表面区域处的金属种子层的部分进料的体电镀电流传导到 金属种子层在半导体晶片的内/中心表面区域，以实现跨晶片的芯片区域中金属电镀的均匀性。

公开(公告)号：US20090194817A1

公开(公告)日：2009-08-06

申请号：US12420936

申请日：2009-04-09

Applicant: Kyoung-woo Lee ,  Ja-hum Ku ,  Jae-eon Park

Inventor： Kyoung-woo Lee ,  Ja-hum Ku ,  Jae-eon Park

IPC: H01L27/092 ,  H01L23/48

CPC classification number: H01L21/823807 ,  H01L21/76816 ,  H01L21/823871 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming CMOS integrated circuit devices include forming at least first, second and third transistors in a semiconductor substrate and then covering the transistors with one or more electrically insulating layers that impart a net stress (tensile or compressive) to channel regions of the transistors. The covering step may include covering the first and second transistors with a first electrically insulating layer having a sufficiently high internal stress characteristic to impart a net tensile (or compressive) stress in a channel region of the first transistor and covering the second and third transistors with a second electrically insulating layer having a sufficiently high internal stress characteristic to impart a net compressive (or tensile) stress in a channel region of the third transistor. A step may then performed to selectively remove a first portion of the second electrically insulating layer extending opposite a gate electrode of the second transistor. In addition, a step may be performed to selectively remove a first portion of the first electrically insulating layer extending opposite a gate electrode of the first transistor and a second portion of the second electrically insulating layer extending opposite a gate electrode of the third transistor.

Abstract translation: 形成CMOS集成电路器件的方法包括在半导体衬底中形成至少第一，第二和第三晶体管，然后用一个或多个赋予晶体管沟道区的净应力（拉伸或压缩）的电绝缘层覆盖晶体管。 覆盖步骤可以包括用具有足够高的内应力特性的第一电绝缘层覆盖第一和第二晶体管，以在第一晶体管的沟道区域中施加净拉伸（或压缩）应力，并用第 具有足够高的内应力特性的第二电绝缘层，以在第三晶体管的沟道区域中施加净压缩（或拉伸）应力。 然后执行步骤以选择性地去除与第二晶体管的栅电极相对延伸的第二电绝缘层的第一部分。 此外，可以执行步骤以选择性地去除与第一晶体管的栅极相对延伸的第一电绝缘层的第一部分和与第三晶体管的栅电极相对延伸的第二电绝缘层的第二部分。

公开(公告)号：US07544996B2

公开(公告)日：2009-06-09

申请号：US11498195

申请日：2006-08-03

Applicant: Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

Inventor： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

IPC: H01L29/94 ,  H01L29/78

CPC classification number: H01L21/823437 ,  H01L21/28247 ,  H01L29/4941 ,  H01L29/6656

Abstract: A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).

Abstract translation: 提供一种制造具有金属栅极图案的半导体器件的方法，其中使用覆盖层来控制氧化过程中金属栅极图案的部分的相对氧化率。 覆盖层可以是多层结构，并且可以被蚀刻以在金属栅极图案的侧壁上形成绝缘间隔物。 封盖层允许使用选择性氧化工艺，其可以是在富H2气氛中使用H 2 O和H 2的分压的湿式氧化工艺，以氧化基板和金属栅极图案的部分，同时抑制 可以包括在金属栅极图案中的金属层的氧化。 这允许对硅衬底的蚀刻损伤和金属栅极图案的边缘减小，同时基本上保持栅极绝缘层的原始厚度和金属层的导电性。

公开(公告)号：US07501651B2

公开(公告)日：2009-03-10

申请号：US11243595

申请日：2005-10-05

Applicant: Min-chul Sun ,  Ja-hum Ku ,  Brian J. Greene ,  Manfred Eller ,  Roman Knoefler ,  Zhijiong Luo

Inventor： Min-chul Sun ,  Ja-hum Ku ,  Brian J. Greene ,  Manfred Eller ,  Roman Knoefler ,  Zhijiong Luo

IPC: H01L23/58

CPC classification number: G01R31/2884 ,  H01L22/34

Abstract: A test structure of a semiconductor device with improved test reliability is provided. The test structure includes first and second active regions which are electrically isolated from each other and on which silicided first and second junction regions are formed, respectively, a semiconductor substrate or a well which is formed on lower parts of the first and second junction regions and has a conductivity type different from the first and second junction regions, and first and second pads through which an electrical signal is applied to the first and second junction regions and detected, and which are formed on the same level as a lower part of a metal layer or on the same level as the semiconductor substrate.

Abstract translation: 提供了具有改善的测试可靠性的半导体器件的测试结构。 测试结构包括彼此电隔离并且分别在其上形成有硅化的第一和第二结区的第一和第二有源区，形成在第一和第二结区的下部的半导体衬底或阱，以及 具有不同于第一和第二接合区域的导电类型，以及第一和第二焊盘，电信号通过该第一和第二焊盘施加到第一和第二接合区域并被检测，并且形成在与金属的下部相同的高度上 层或与半导体衬底相同的水平。

公开(公告)号：US20090017630A1

公开(公告)日：2009-01-15

申请号：US11778039

申请日：2007-07-14

Applicant: Kyoung Woo Lee ,  Ja Hum Ku ,  WanJae Park ,  Chong Kwang Chang ,  Theodorus E. Standaert

Inventor： Kyoung Woo Lee ,  Ja Hum Ku ,  WanJae Park ,  Chong Kwang Chang ,  Theodorus E. Standaert

IPC: H01L21/311

CPC classification number: H01L21/76816 ,  H01L21/76829 ,  H01L21/823807 ,  H01L21/823871

Abstract: Semiconductor fabrication methods to forma of via contacts in DSL (dual stress liner) semiconductor devices are provided, in which improved etching process flows are implemented to enable etching of via contact openings through overlapped and non-overlapped regions of the dual stress liner structure to expose underlying salicided contacts and other device contacts, while mitigating or eliminating defect mechanisms such as over etching of contact regions underlying non-overlapped regions of the DSL.

Abstract translation: 提供了在DSL（双重应力衬垫）半导体器件中形成通孔接触的半导体制造方法，其中实现改进的蚀刻工艺流程，以便能够通过双重应力衬垫结构的重叠和非重叠区域蚀刻通孔接触开口以暴露 底层的水银触点和其他设备触点，同时减轻或消除缺陷机制，例如对DSL的非重叠区域下的接触区域进行过蚀刻。

公开(公告)号：US07435673B2

公开(公告)日：2008-10-14

申请号：US11237987

申请日：2005-09-28

Applicant: Kyoung Woo Lee ,  Ja-Hum Ku ,  Duk Ho Hong ,  Wan Jae Park

Inventor： Kyoung Woo Lee ,  Ja-Hum Ku ,  Duk Ho Hong ,  Wan Jae Park

IPC: H01L21/4763

CPC classification number: H01L21/7684 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76877

Abstract: Methods of forming metal interconnect structures include forming a first electrically insulating layer on a semiconductor substrate and forming a second electrically insulating layer on the first electrically insulating layer. The second and first electrically insulating layers are selectively etched in sequence to define a contact hole therein. A first metal layer (e.g., tungsten) is deposited. This first metal layer extends on the second electrically insulating layer and into the contact hole. The first metal layer is then patterned to expose the second electrically insulating layer. The second electrically insulating layer is selectively etched for a sufficient duration to expose the first electrically insulating layer and expose a metal plug within the contact hole. This selective etching step is performed using the patterned first metal layer as an etching mask. A seam within the exposed metal plug is then filled with an electrically conductive filler material (e.g., CoWP). A second metal layer is then formed on the exposed metal plug containing the electrically conductive filler material.

Abstract translation: 形成金属互连结构的方法包括在半导体衬底上形成第一电绝缘层，并在第一电绝缘层上形成第二电绝缘层。 依次选择性地蚀刻第二和第一电绝缘层以在其中限定接触孔。 沉积第一金属层（例如钨）。 该第一金属层在第二电绝缘层上延伸并进入接触孔。 然后将第一金属层图案化以暴露第二电绝缘层。 选择性地蚀刻第二电绝缘层足够的持续时间以暴露第一电绝缘层并在接触孔内露出金属插塞。 使用图案化的第一金属层作为蚀刻掩模来执行该选择性蚀刻步骤。 暴露的金属插头内的接缝然后用导电填充材料（例如，CoWP）填充。 然后在暴露的包含导电填料的金属塞上形成第二金属层。

公开(公告)号：US20080124859A1

公开(公告)日：2008-05-29

申请号：US11563476

申请日：2006-11-27

Applicant: Min Chul Sun ,  Jong Ho Yang ,  Young Gun Ko ,  Ja Hum Ku ,  Jae Eon Park ,  Jeong Hwan Yang ,  Christopher Vincent Baiocco ,  Gerald Leake

Inventor： Min Chul Sun ,  Jong Ho Yang ,  Young Gun Ko ,  Ja Hum Ku ,  Jae Eon Park ,  Jeong Hwan Yang ,  Christopher Vincent Baiocco ,  Gerald Leake

IPC: H01L21/8238 ,  H01L21/336

CPC classification number: H01L21/823864

Abstract: Methods of forming field effect transistors include methods of forming PMOS and NMOS transistors by forming first and second gate electrodes on a substrate and then forming an electrically insulating layer having etch-enhancing impurities therein, on the first and second gate electrodes. The electrically insulating layer may be formed as a boron-doped silicon nitride layer or an electrically insulating layer that is doped with germanium and/or fluorine. The electrically insulating layer is etched-back to define first sidewall spacers on the first gate electrode and second sidewall spacers on the second gate electrode. P-type source and drain region dopants are then implanted into the semiconductor substrate, using the first sidewall spacers as a first implant mask. The second sidewall spacers on the second gate electrode are then etched back to reduce their lateral dimensions. N-type source and drain region dopants are then implanted into the semiconductor substrate, using the second sidewall spacers with reduced lateral dimensions as a second implant mask.

Abstract translation: 形成场效应晶体管的方法包括通过在衬底上形成第一和第二栅电极，然后在第一和第二栅电极上形成其中具有蚀刻增强杂质的电绝缘层来形成PMOS和NMOS晶体管的方法。 电绝缘层可以形成为掺杂硼的氮化硅层或掺杂有锗和/或氟的电绝缘层。 电绝缘层被回蚀刻以限定第一栅电极上的第一侧壁间隔物和第二栅电极上的第二侧壁间隔物。 然后，使用第一侧壁间隔物作为第一注入掩模将P型源区和漏区掺杂剂注入到半导体衬底中。 然后将第二栅电极上的第二侧壁间隔物回蚀以减小其横向尺寸。 然后使用具有减小的横向尺寸的第二侧壁间隔作为第二植入掩模将N型源区和漏区掺杂剂注入到半导体衬底中。

公开(公告)号：US20080093746A1

公开(公告)日：2008-04-24

申请号：US11551864

申请日：2006-10-23

Applicant: Kyoung Woo Lee ,  Ja Hum Ku ,  Ki Chul Park ,  Seung Man Choi

Inventor： Kyoung Woo Lee ,  Ja Hum Ku ,  Ki Chul Park ,  Seung Man Choi

IPC: H01L23/52 ,  H01L21/4763

CPC classification number: H01L23/53238 ,  H01L21/2885 ,  H01L23/564 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor wafer having multi-layer metallization structures that are fabricated to include embedded interconnection structures which serve as low-resistance electroplating current paths to conduct bulk electroplating current fed to portions of a metallic seed layer at peripheral surface regions of the wafer to portions of the metallic seed layer at inner/central surface regions of the semiconductor wafer to achieve uniformity in metal plating in chip regions across the wafer.

Abstract translation: 具有多层金属化结构的半导体晶片，其被制造为包括用作低电阻电镀电流路径的嵌入式互连结构，以将在晶片的外围表面区域处的金属种子层的部分进料的体电镀电流传导到 金属种子层在半导体晶片的内/中心表面区域，以实现跨晶片的芯片区域中金属电镀的均匀性。