公开(公告)号：US09201654B2

公开(公告)日：2015-12-01

申请号：US13171027

申请日：2011-06-28

申请人： Jason F. Cantin ,  Jack R. Smith ,  Arnold S. Tran ,  Kenichi Tsuchiya

发明人： Jason F. Cantin ,  Jack R. Smith ,  Arnold S. Tran ,  Kenichi Tsuchiya

IPC分类号： G06F9/38

CPC分类号： G06F9/3806 ,  G06F9/3848

摘要： Disclosed are a processor and a processing method incorporating an instruction pipeline with direction prediction (i.e., taken or not taken) for conditional branch instructions. In the embodiments, reading of a branch instruction history table (BHT) and a branch instruction target address cache (BTAC) for branch direction prediction occurs in parallel with the current instruction fetch in order to minimize delay in the next instruction fetch. Additionally, direction prediction is performed in the very next clock cycle based either on an initial direction prediction for the specific instruction, as stored in the BHT, or, if applicable, on a prior entry for the specific instruction in the BTAC. An override bit associated with each entry in the BTAC is the determining factor for whether or the BTAC or BHT is controlling. Override bits in the BTAC can be pre-established based on the branch instruction type in order to ensure prediction accuracy.

摘要翻译： 公开了一种处理器和处理方法，其结合了用于条件分支指令的具有方向预测（即采取或未采用）的指令流水线。 在实施例中，用于分支方向预测的分支指令历史表（BHT）和分支指令目标地址高速缓存（BTAC）的读取与当前指令获取并行发生，以便使下一指令提取中的延迟最小化。 另外，方向预测是在下一个时钟周期内执行的，即基于存储在BHT中的特定指令的初始方向预测，或者如果适用，在BTAC中针对特定指令的先前条目。 与BTAC中的每个条目相关联的覆盖位是否是BTAC或BHT正在控制的决定因素。 可以基于分支指令类型预先建立BTAC中的覆盖位，以确保预测精度。

公开(公告)号：US08756549B2

公开(公告)日：2014-06-17

申请号：US12984638

申请日：2011-01-05

申请人： Richard S. Graf ,  Keishi Okamoto ,  Faraydon Pakbaz ,  Jack R. Smith ,  Sebastian T. Ventrone

发明人： Richard S. Graf ,  Keishi Okamoto ,  Faraydon Pakbaz ,  Jack R. Smith ,  Sebastian T. Ventrone

IPC分类号： G06F17/50 ,  G06F9/455 ,  G06F19/00 ,  G01R31/02 ,  G01R31/00 ,  G01R31/26 ,  H03K5/22

CPC分类号： H05B1/0227 ,  G05D23/1934

摘要： Disclosed are embodiments of an integrated circuit chip designed for reliability at low ambient temperatures. The chip substrate can be divided into zones, including at least one temperature-sensitive zone (TSZ) that contains one or more temperature-sensitive circuits. Temperature sensor(s) can be positioned in the semiconductor substrate adjacent to the TSZ. Thermal radiator(s) can be embedded in a metal wiring layer and aligned above the TSZ. The temperature sensor(s) can be operatively connected to the thermal radiator(s) and can trigger operation of the thermal radiator(s) when the temperature in the TSZ is below a predetermined threshold temperature. Additionally, an on-chip power control system can be operatively connected to the thermal radiator(s) so that operation of the thermal radiator(s) is only triggered when a circuit within the TSZ is about to be powered up. Also disclosed are associated embodiments of a system and method for designing such an integrated circuit chip.

摘要翻译： 公开了设计用于在低环境温度下可靠性的集成电路芯片的实施例。 芯片基板可以分为包括至少一个包含一个或多个温度敏感电路的至少一个温度敏感区（TSZ）的区域。 温度传感器可以位于与TSZ相邻的半导体衬底中。 热辐射器可以嵌入在金属布线层中，并在TSZ上方对齐。 温度传感器可以可操作地连接到散热器，并且当TSZ中的温度低于预定阈值温度时，可以触发热辐射器的操作。 此外，片上功率控制系统可以可操作地连接到散热器，使得热辐射器的操作仅在TSZ内的电路即将被加电时触发。 还公开了用于设计这种集成电路芯片的系统和方法的相关实施例。

公开(公告)号：US08381050B2

公开(公告)日：2013-02-19

申请号：US12625703

申请日：2009-11-25

申请人： Pamela S. Gillis ,  Jack R. Smith ,  Tad J. Wilder ,  Francis Woytowich ,  Tian Xia

发明人： Pamela S. Gillis ,  Jack R. Smith ,  Tad J. Wilder ,  Francis Woytowich ,  Tian Xia

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G06F1/10 ,  G01R31/318544 ,  G01R31/318552 ,  G01R31/318594

摘要： The invention disclosed herein provides increased effectiveness of delay and transition fault testing. The method of delay fault testing integrated circuits comprises the steps of creating a plurality of test clock gating groups. The plurality of test clock gating groups comprising elements defining inter-element signal paths within the integrated circuit. Each of the elements of the plurality of test clock gating groups share clock frequency and additional shared characteristics. At least one test signal is commonly and selectively connected through at least one low-speed gate transistor to each of the elements comprising each of the plurality of test clock gating groups based on membership in the test clock gating group. This invention can also be practiced using scan-enable gating groups for the same purposes.

摘要翻译： 本文公开的发明提供了延迟和转换故障测试的增加的有效性。 延迟故障测试集成电路的方法包括创建多个测试时钟门控组的步骤。 多个测试时钟门控组包括限定集成电路内的元件间信号路径的元件。 多个测试时钟选通组中的每个元件共享时钟频率和额外的共享特性。 基于测试时钟选通组的成员资格，至少一个测试信号通过至少一个低速栅极晶体管被共同且选择性地连接到包括多个测试时钟门控组中的每一个的每个元件。 为了相同的目的，本发明也可以使用扫描启用门控组来实现。

公开(公告)号：US20120062300A1

公开(公告)日：2012-03-15

申请号：US12882425

申请日：2010-09-15

申请人： Michael R. Ouellette ,  Faraydon Pakbaz ,  Jack R. Smith ,  Sebastian T. Ventrone

发明人： Michael R. Ouellette ,  Faraydon Pakbaz ,  Jack R. Smith ,  Sebastian T. Ventrone

IPC分类号： H03H11/26

CPC分类号： G06F5/10 ,  G06F2205/104

摘要： Disclosed are embodiments of an asynchronous pipeline circuit. In each stage of the circuit, a variable delay line is incorporated into the request signal path. A tap encoder monitors data entering the stage to detect any state changes occurring in specific data bits. Based on the results of this monitoring (i.e., based on which of the specific data bits, if any, exhibit state changes), the tap encoder enables a specific tap in the variable delay line and, thereby, automatically adjusts the delay of a request signal transmitted along the request signal path. Using a variable request signal delay allows data from a transmitting stage to be captured by a receiving stage prior to the expiration of the maximum possible processing time associated with the transmitting stage, thereby minimizing overall processing time. Also disclosed are embodiments of methods for asynchronous pipeline processing with variable request signal delay and for incorporating variable request signal delay into an asynchronous pipeline circuit design.

摘要翻译： 公开了异步管线电路的实施例。 在电路的每个阶段，可变延迟线被并入到请求信号路径中。 抽头编码器监视进入阶段的数据，以检测在特定数据位中发生的任何状态变化。 基于该监视的结果（即，基于特定数据位中的哪一个，如果有的话，表现出状态改变），则分接编码器在可变延迟线中启用特定抽头，从而自动调整请求的延迟 信号沿请求信号路径传输。 使用可变请求信号延迟允许在与发送级相关联的最大可能处理时间到期之前由接收级捕获来自发送级的数据，从而最小化整个处理时间。 还公开了用于具有可变请求信号延迟的异步流水线处理的方法的实施例，并且将可变请求信号延迟并入到异步管线电路设计中。

公开(公告)号：US20110307661A1

公开(公告)日：2011-12-15

申请号：US12796990

申请日：2010-06-09

申请人： Jack R. SMITH ,  Sebastian T. VENTRONE

发明人： Jack R. SMITH ,  Sebastian T. VENTRONE

IPC分类号： G06F15/76 ,  G06F13/24 ,  G06F9/02 ,  G06F12/08

CPC分类号： G06F12/0855 ,  G06F15/7878

摘要： An integrated circuit chip having plural processors with a shared field programmable gate array (FPGA) unit, a design structure thereof, and method for allocating the shared FPGA unit. A method includes storing a plurality of data that define a plurality of configurations of a field programmable gate array (FPGA), wherein the FPGA is arranged in the execution pipeline of at least one processor; selecting one of the plurality of data; and programming the FPGA based on the selected one of the plurality of data.

摘要翻译： 一种集成电路芯片，具有具有共享现场可编程门阵列（FPGA）单元的多个处理器，其设计结构以及用于分配共享FPGA单元的方法。 一种方法包括存储定义现场可编程门阵列（FPGA）的多个配置的多个数据，其中FPGA布置在至少一个处理器的执行流水线中; 选择所述多个数据中的一个; 以及基于所述多个数据中选择的一个来编程所述FPGA。

公开(公告)号：US07417453B2

公开(公告)日：2008-08-26

申请号：US11181053

申请日：2005-07-14

申请人： Kenneth J Goodnow ,  Clarence R Ogilvie ,  Christopher B Reynolds ,  Jack R Smith ,  Sebastian T Ventrone

发明人： Kenneth J Goodnow ,  Clarence R Ogilvie ,  Christopher B Reynolds ,  Jack R Smith ,  Sebastian T Ventrone

IPC分类号： H03K19/173

CPC分类号： H03K19/17752 ,  G06F15/7867 ,  H03K19/17756 ,  H03K19/1776

摘要： A reconfigurable logic array (RLA) system (104) that includes an RLA (108) and a programmer (112) for reprogramming the RLA on a cyclical basis. A function (F) requiring a larger amount of logic than contained in the RLA is partitioned into multiple functional blocks (FB1, FB2, FB3). The programmer contains software (144) that partitions the RLA into a function region FR located between two storage regions SR1, SR2. The programmer then programs functional region sequentially with the functional blocks of the function so that the functional blocks process in alternating directions between the storage regions. While the programmer is reconfiguring function region with the next functional block and reconfiguring one of the storage regions for receiving the output of the next functional block, data being passed from the current functional block to the next functional block is held in the other storage region.

摘要翻译： 一种可重构逻辑阵列（RLA）系统（104），包括RLA（108）和编程器（112），用于循环地重新编程RLA。 需要比RLA中包含的逻辑大的功能（F）被划分为多个功能块（FB 1，FB 2，FB 3）。 程序员包含将RLA分割成位于两个存储区域SR 1，SR 2之间的功能区域FR的软件（144）。 然后，程序员用功能块的功能块顺序地对功能区进行编程，使得功能块在存储区之间交替地进行处理。 当编程器用下一个功能块重新配置功能区域并且重新配置存储区域之一以接收下一个功能块的输出时，从当前功能块传递到下一个功能块的数据被保存在另一个存储区域中。

公开(公告)号：US07304493B2

公开(公告)日：2007-12-04

申请号：US11371833

申请日：2006-03-09

申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Jack R. Smith ,  Sebastian T. Ventrone ,  Keith R. Williams

发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Jack R. Smith ,  Sebastian T. Ventrone ,  Keith R. Williams

IPC分类号： H03K19/00

CPC分类号： H03K19/177

摘要： A field programmable gate array (FPGA) device including a non-programming-based default power-on electronic configuration. The non-programming-based default power-on electronic configuration defines a default state to initial a first logic function. Upon power-up, the FPGA device would be enabled to enter the default state without having first to be configured via a conventional programming mode, thus saving processing time during power-up. Several embodiments are disclosed, such as a mask via circuit, an asynchronous set/reset circuit, an unbalanced latch circuit and a flush and scan circuit. A related method is also disclosed to reduce the memory size dedicated to the first logic function to facilitate further programming after power-up. In addition to time saving and further programming, the FPGA device can also allow partial or incremental programming to expand the full functionality to match customer's different needs.

公开(公告)号：US07134104B2

公开(公告)日：2006-11-07

申请号：US10707323

申请日：2003-12-05

申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Jack R. Smith ,  Sebastian T. Ventrone

发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Jack R. Smith ,  Sebastian T. Ventrone

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F11/18

摘要： A new hardware description language (HDL) extension at the register-transfer level (RTL) for designating particular logic functions as fault tolerant and a method of implementing a fault redundant scheme for the fault tolerant logic functions. Code (20) is written in VHDL at the RTL and includes instructions for adding the operator “FT” to certain logic functions. Logic functions that include the FT operator are considered critical functions, i.e., fault tolerant. By including the FT operator, a logic synthesis tool is alerted to the functions that have been designated as fault tolerant. As a result, the preprogrammed logic synthesis tool causes the design of the IC to include a fault redundant scheme (30) for the logic functions that include the FT operator. Fault redundant scheme (30) includes three copies of the logic function, i.e., Copy A (32), Copy B (34), and Copy C (36), as well as a majority voter 38.

摘要翻译： 用于指定特定逻辑功能作为容错的寄存器传输级（RTL）的新硬件描述语言（HDL）扩展以及为容错逻辑功能实现故障冗余方案的方法。 代码（20）以RTL写入VHDL，并包括将操作符“FT”添加到某些逻辑功能的指令。 包括FT操作员的逻辑功能被认为是关键功能，即容错。 通过包括FT操作员，逻辑综合工具被提醒已被指定为容错的功能。 因此，预编程的逻辑综合工具使得IC的设计包括用于包括FT操作员的逻辑功能的故障冗余方案（30）。 故障冗余方案（30）包括逻辑功能的三个副本，即复制A（32），复制B（34）和复制C（36）以及多数选民38。

公开(公告)号：US4160362A

公开(公告)日：1979-07-10

申请号：US783248

申请日：1977-03-31

申请人： Alan Martens ,  Thomas J. Radkevich ,  Jack R. Smith

发明人： Alan Martens ,  Thomas J. Radkevich ,  Jack R. Smith

IPC分类号： F02C3/30 ,  F02C7/02 ,  F02C9/02

CPC分类号： F02C3/30 ,  Y02E20/16

摘要： A combined cycle power plant includes a gas turbine and an afterburner to which fuel is supplied for speed and load control. Water is injected into the turbine combustors by a controlled water injection system to control total NOx emissions from the turbine and the afterburner as a function of turbine load corrected for changes in inlet air temperature and inlet guide vane position.

摘要翻译： 联合循环发电厂包括一个燃气轮机和一个燃料加速器，燃料供应给燃料涡轮机以加速和负载控制。 通过受控的注水系统将水注入到涡轮燃烧器中，以根据对入口空气温度和入口引导叶片位置的变化进行校正的涡轮机负荷来控制来自涡轮机和后燃器的总NOx排放。

公开(公告)号：US3978659A

公开(公告)日：1976-09-07

申请号：US551203

申请日：1975-02-19

申请人： Jack R. Smith ,  Leonard H. Burrows

发明人： Jack R. Smith ,  Leonard H. Burrows

IPC分类号： F02C9/00 ,  F02C9/08

CPC分类号： F02C9/00

摘要： A backup control system for a gas turbine power plant having a computer implemented primary control system is disclosed. Bumpless transfer between the two control systems is effected by tracking a plurality of control signals generated by each control system, the signals being functionally identical, but independent. After comparison of the functionally identical signals, transfer between the two control systems is permitted only if any tracking error does not exceed a permissible deadband margin.The presence of tracking error is also utilized to generate a signal which is employed to operate panel mounted signal means, which panel can thereby be used as a diagnostic tool in monitoring the health of both the primary and backup systems. Transfer reliability is thereby enhanced and turbine availability improved.

摘要翻译： 公开了一种具有计算机实现的主控制系统的燃气轮机发电厂的备用控制系统。 通过跟踪由每个控制系统产生的多个控制信号，这些信号在功能上是相同的，但是独立的，可以实现两个控制系统之间的无级传输。 在比较功能相同的信号之后，只有在任何跟踪误差不超过允许的死区余量时才允许两个控制系统之间进行传输。