公开(公告)号：US20130135910A1

公开(公告)日：2013-05-30

申请号：US13591580

申请日：2012-08-22

申请人： Sang Hyun MIN ,  Koon Shik Cho ,  Jae Hyung Lee ,  Kwang Mook Lee

发明人： Sang Hyun MIN ,  Koon Shik Cho ,  Jae Hyung Lee ,  Kwang Mook Lee

IPC分类号： G05F1/70 ,  H02M7/06

CPC分类号： H02M1/4225 ,  H02M2001/0003 ,  Y02B70/126 ,  Y02P80/112

摘要： There are provided a power factor correction apparatus, a direct current/direct current (DC/DC) converter, and a power supplying apparatus, capable of preventing unstable feedback control due to a ripple component by controlling power switching based on a median value between a maximum value and a minimum value of a voltage level of the output power that is received as feedback. The power factor correction apparatus includes a power factor corrector switching input power and correcting a power factor thereof; and a controller detecting a voltage level of power factor-corrected power and controlling the switching of the power factor corrector, based on a median value between a maximum value and a minimum value of the voltage level of the power factor-corrected power detected for a predetermined period of time.

摘要翻译： 提供了功率因数校正装置，直流/直流（DC / DC）转换器和供电装置，其能够通过基于中间值控制功率切换来防止由于纹波分量引起的不稳定的反馈控制 作为反馈接收的输出功率的电压电平的最大值和最小值。 功率因数校正装置包括功率因数校正器切换输入功率并校正其功率因数; 以及控制器，其基于所检测的功率因数校正功率的电压电平的最大值和最小值之间的中值，检测功率因数校正功率的电压电平并控制功率因数校正器的切换， 预定时间段。

公开(公告)号：US08184742B2

公开(公告)日：2012-05-22

申请号：US12137463

申请日：2008-06-11

申请人： U Sang Lee ,  Jae Hyung Lee ,  Sang Ho Lee ,  Kwang Mook Lee

发明人： U Sang Lee ,  Jae Hyung Lee ,  Sang Ho Lee ,  Kwang Mook Lee

IPC分类号： H03K9/00 ,  H04L27/00

CPC分类号： H04L7/043 ,  H04B1/7075

摘要： A preprocessing unit samples and digitalizes analog signal. A differential operation unit delays digitalized signal for a predetermined period and differentiates delayed signals. A correlation unit correlates differentiated signal with a plurality of predetermined PN code sequences. A setting unit includes a shift register having a plurality of storage locations for shifting the correlation values and sequentially storing shifted correlation values at the storage locations, respectively, a detector including the determination slots for detecting the storage location of the maximum value, and a slot setter for comparing the storage location of the maximum value from the detector with the predetermined reference storage location and shifting the determination slots by the difference therebetween. A demodulation value estimation unit estimates, as a demodulation value of the received analog signal, a symbol of a PN code sequence corresponding to the maximum value from the shifted determination slots.

摘要翻译： 预处理单元对模拟信号进行采样和数字化。 差分操作单元在预定时间段内延迟数字化信号并区分延迟信号。 相关单元将微分信号与多个预定PN码序列相关联。 一个设置单元包括一个移位寄存器，它具有多个存储位置，用于移位相关值，并分别在存储位置依次存储偏移的相关值;检测器，包括用于检测最大值的存储位置的确定时隙; 用于将来自检测器的最大值的存储位置与预定参考存储位置进行比较，并且将确定时隙移位其间的差。 解调值估计单元从所述移位的确定时隙估计与所接收的模拟信号的解调值相对应的最大值的PN码序列的符号。

公开(公告)号：USD619177S1

公开(公告)日：2010-07-06

申请号：US29322111

申请日：2008-07-29

申请人： Jae-Hyung Lee

设计人： Jae-Hyung Lee

公开(公告)号：US20100138419A1

公开(公告)日：2010-06-03

申请号：US12598200

申请日：2008-07-18

申请人： Kil-Youn Kim ,  Sun-Ok Cho ,  Dae-Bong Park ,  Jae-Hyung Lee

发明人： Kil-Youn Kim ,  Sun-Ok Cho ,  Dae-Bong Park ,  Jae-Hyung Lee

IPC分类号： G06F17/30 ,  G06F3/00

CPC分类号： G06F16/71 ,  G06F16/738 ,  G06F16/78

摘要： A method of providing a moving picture search service and an apparatus therefor are disclosed. An embodiment of the present invention provides a method of providing a moving picture search service that includes: obtaining a search keyword from a client terminal; and providing as search results a moving picture cluster list displaying information about a moving picture cluster matching with the search keyword. The moving picture cluster includes a plurality of moving pictures determined to have identity, and the moving picture cluster list includes a cluster unit display area displaying information about the moving picture cluster differently from information about another moving picture cluster included in the moving picture cluster list. By providing moving picture search results related to a search keyword in groups of cluster units, users can understand the search results more easily.

摘要翻译： 公开了一种提供运动图像搜索服务的方法及其装置。 本发明的实施例提供一种提供运动图像搜索服务的方法，包括：从客户终端获取搜索关键字; 并且作为搜索结果提供显示关于与搜索关键词匹配的运动图像集群的信息的运动图像集群列表。 运动图像群集包括被确定为具有身份的多个运动图像，并且运动图像簇列表包括不同于关于运动图像簇列表中所包括的另一个运动图像簇的信息，显示关于运动图像簇的信息的簇单位显示区域。 通过以群集为单位提供与搜索关键字相关的运动图像搜索结果，用户可以更容易地了解搜索结果。

公开(公告)号：US20100110913A1

公开(公告)日：2010-05-06

申请号：US12347846

申请日：2008-12-31

申请人： Sang Hyun Min ,  Soon Jin Choi ,  Jae Hyung Lee ,  Sang Ho Lee ,  Kwang Mook Lee

发明人： Sang Hyun Min ,  Soon Jin Choi ,  Jae Hyung Lee ,  Sang Ho Lee ,  Kwang Mook Lee

IPC分类号： H04L12/26

CPC分类号： H04B17/345 ,  H04L43/16

摘要： The present invention relates to a method for detecting interference and an interference detecting device for a wireless communication capable of improving detection accuracy of an interference signal in a wireless communication device without influencing network operation while the interference signal is detected; and, more particularly, to a method for detecting interference and an interference detecting device for a wireless communication to determine an interference signal by increasing an interference packet count according to an RSSI value, its own packet detection, gain reduction, deterioration of signal quality, the number of the same symbols, and so on and comparing an increased interference packet count value with a threshold value by using each ZigBee device as a main constituent of interference detection unlike a conventional method for detecting interference in which a ZigBee coordinator or a ZigBee router is a main constituent of interference detection.

摘要翻译： 本发明涉及一种用于检测干扰的方法和用于无线通信的干扰检测装置，其能够在检测到干扰信号的同时不影响网络操作，提高无线通信装置中的干扰信号的检测精度; 更具体地，涉及一种用于检测干扰的方法和用于无线通信的干扰检测装置，以通过根据RSSI值，其自身的分组检测，增益减小，信号质量的劣化增加干扰分组计数来确定干扰信号， 相同符号的数量等，并且通过使用每个ZigBee设备作为干扰检测的主要成分，将增加的干扰分组计数值与阈值进行比较，这与传统的用于检测干扰的方法不同，ZigBee协调器或ZigBee路由器 是干扰检测的主要成分。

公开(公告)号：US07492623B2

公开(公告)日：2009-02-17

申请号：US11655966

申请日：2007-01-22

申请人： Jae-Hyung Lee

发明人： Jae-Hyung Lee

IPC分类号： G11C17/00

CPC分类号： G11C7/1045 ,  G11C17/14 ,  G11C29/028 ,  G11C29/46 ,  G11C2029/4402

摘要： An option circuit of a semiconductor chip includes a first option circuit that is set before packaging the semiconductor chip to generate a first option signal; a second option circuit that is set after packaging the semiconductor chip to generate a second option signal; and a selection circuit configured to: select one of the first option signal, the second option signal, and a mode register set signal in response to at least one first control signal; and output a first selected signal as a final option signal. An option method of a semiconductor chip includes setting a first option mode of the semiconductor chip by use of the first option circuit; setting a second option mode of the semiconductor chip by use of the second option circuit; and determining a final option mode of the semiconductor chip by selection of the first option mode or the second option mode.

摘要翻译： 半导体芯片的选择电路包括在封装半导体芯片之前设置以产生第一选项信号的第一选择电路; 在封装半导体芯片以产生第二选项信号之后设置的第二选择电路; 以及选择电路，被配置为：响应于至少一个第一控制信号，选择第一选项信号，第二选择信号和模式寄存器设置信号之一; 并输出第一选定信号作为最终选择信号。 半导体芯片的选择方法包括使用第一选择电路设置半导体芯片的第一选项模式; 通过使用第二选择电路设置半导体芯片的第二选择模式; 以及通过选择所述第一选项模式或所述第二选项模式来确定所述半导体芯片的最终选择模式。

公开(公告)号：US20070044055A1

公开(公告)日：2007-02-22

申请号：US11379030

申请日：2006-04-17

申请人： In-Soo PARK ,  Jae-Hyung LEE

发明人： In-Soo PARK ,  Jae-Hyung LEE

IPC分类号： G06F17/50

CPC分类号： G06F1/04 ,  G06F1/10 ,  H03K5/1565

摘要： A clock signal driver and a clock signal supplying circuit having the same are provided. An embodiment of the clock signal driver includes an internal clock driver for receiving a clock signal and a complementary clock signal, buffering the clock signal and inverting the complementary clock signal, and combining phases of the buffered clock signal and the inverted complementary clock signal to generate an internal clock signal. And the clock signal driver further includes a complementary internal clock driver for receiving the clock signal and the complementary clock signal, inverting the clock signal and buffering the complementary clock signal, and combining phases of the inverted clock signal and the buffered complementary clock signal to generate a complementary internal clock signal.

摘要翻译： 提供了具有该时钟信号驱动器和时钟信号提供电路的时钟信号驱动器。 时钟信号驱动器的实施例包括用于接收时钟信号和互补时钟信号的内部时钟驱动器，缓冲时钟信号并使互补时钟信号反相，以及组合缓冲时钟信号和反相互补时钟信号的相位以产生 内部时钟信号。 并且时钟信号驱动器还包括互补的内部时钟驱动器，用于接收时钟信号和互补时钟信号，反相时钟信号和缓冲互补时钟信号，以及组合反相时钟信号和缓冲的互补时钟信号的相位以产生 互补的内部时钟信号。

公开(公告)号：US06954094B2

公开(公告)日：2005-10-11

申请号：US10645018

申请日：2003-08-21

申请人： Jae-hyung Lee ,  Kyu-hyoun Kim

发明人： Jae-hyung Lee ,  Kyu-hyoun Kim

IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/407 ,  G11C11/4076 ,  H03K5/13 ,  H03L7/06

CPC分类号： G11C7/1066 ,  G11C7/1045 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076

摘要： A semiconductor memory device having a partially controlled delay locked loop includes a delay locked loop and a control signal generator. The control signal generator generates a first control signal and a second control signal, which are responsive to first through fifth mode selection signals for selecting operation modes of the semiconductor memory, device to partially turn the delay locked loop on or off. If the first control signal or the second control signal is activated, a portion of the delay locked loop to which the first or second control signal is applied is turned off. If the first control signal or the second control signal is deactivated, a portion of the delay locked loop to which the first or second control signal is applied is turned on. If the first mode selection signal is activated, only the second control signal is activated. If the second mode selection signal is activated, the first and second control signals are deactivated. If at least one of the third through fifth mode selection signals is activated, the first and second control signals are activated. Since the semiconductor memory device includes a built-in delay locked loop which is partially turned on or off, current consumption of the semiconductor memory device can be reduced.

摘要翻译： 具有部分控制的延迟锁定环路的半导体存储器件包括延迟锁定环路和控制信号发生器。 所述控制信号发生器产生第一控制信号和第二控制信号，所述第一控制信号和第二控制信号响应于第一至第五模式选择信号，用于选择半导体存储器的操作模式，以部分地将延迟锁定环打开或关闭。 如果第一控制信号或第二控制信号被激活，则施加第一或第二控制信号的延迟锁定环路的一部分被关闭。 如果第一控制信号或第二控制信号被去激活，则施加第一或第二控制信号的延迟锁定环路的一部分被接通。 如果第一模式选择信号被激活，则只有第二控制信号被激活。 如果第二模式选择信号被激活，则第一和第二控制信号被去激活。 如果第三至第五模式选择信号中的至少一个被激活，则第一和第二控制信号被激活。 由于半导体存储器件包括部分导通或截止的内置延迟锁定环，所以可以减少半导体存储器件的电流消耗。

公开(公告)号：US20050017783A1

公开(公告)日：2005-01-27

申请号：US10890493

申请日：2004-07-13

申请人： Jae-hyung Lee ,  Kyu-hyoun Kim

发明人： Jae-hyung Lee ,  Kyu-hyoun Kim

IPC分类号： H03K5/02 ,  H03K3/356 ,  H03K19/003 ,  H03K19/0185 ,  H04L25/02 ,  H04L25/45 ,  H03K3/037

CPC分类号： H04L25/45 ,  H03K3/356104 ,  H03K3/356113 ,  H03K19/00323 ,  H03K19/018521

摘要： Provided are an interface circuit and a signal clamping circuit using a level-down shifter. The interface circuit includes the level-down shifter between a first power circuit driven by a first power and a second power circuit driven by a second power. The level-down shifter converts an output of the first power circuit that has a voltage level of the first power into an output of a voltage level of the second power. The level-down shifter includes a first circuit unit, a second circuit unit, a third circuit unit, and a fourth circuit unit. The first circuit unit is driven by the first power and receives the output of the first power circuit. The second circuit unit is driven by the second power and receives the output of the first power circuit. The third circuit unit is driven by the second power and receives the output of the first power circuit. The fourth circuit unit is driven by the second power, receives an output of the third circuit unit, and is connected to an output of the second circuit unit.

摘要翻译： 提供了使用电平降低移位器的接口电路和信号钳位电路。 接口电路包括由第一电源驱动的第一电源电路和由第二电源驱动的第二电源电路之间的电平降低移位器。 电平降低移位器将具有第一功率的电压电平的第一电源电路的输出转换为第二功率的电压电平的输出。 电平降低移位器包括第一电路单元，第二电路单元，第三电路单元和第四电路单元。 第一电路单元由第一电源驱动并接收第一电源电路的输出。 第二电路单元由第二电源驱动并接收第一电源电路的输出。 第三电路单元由第二电源驱动并接收第一电源电路的输出。 第四电路单元由第二电源驱动，接收第三电路单元的输出，并连接到第二电路单元的输出端。

公开(公告)号：US06845751B2

公开(公告)日：2005-01-25

申请号：US10330382

申请日：2002-12-27

申请人： Jae-Hyung Lee

发明人： Jae-Hyung Lee

IPC分类号： F02D45/00 ,  F02D31/00 ,  F02D35/00 ,  F02D41/08 ,  F02D41/16 ,  F02M69/32

CPC分类号： F02D35/0007 ,  F02D31/005

摘要： In the invention an apparatus and method direct an engine speed to converge to a target idle speed by detecting a current engine speed, calculating a dynamic reference speed based on the current engine speed, calculating a target idle speed actuator (ISA) opening based on the dynamic reference speed and the current engine speed, and actuating the ISA based on the target ISA opening.

摘要翻译： 在本发明中，一种装置和方法，通过检测当前发动机转速，通过检测当前发动机转速来引导发动机速度收敛到目标怠速，基于当前发动机转速计算动态参考速度，基于 动态参考速度和当前发动机转速，并根据目标ISA开启启动ISA。