公开(公告)号：US20090305495A1

公开(公告)日：2009-12-10

申请号：US12465013

申请日：2009-05-13

Applicant: Young-Ho Lee ,  Jae-Hwang Sim ,  Jae-Kwan Park ,  Mo-Seok Kim ,  Jong-Min Lee ,  Dong-Sik Lee

Inventor： Young-Ho Lee ,  Jae-Hwang Sim ,  Jae-Kwan Park ,  Mo-Seok Kim ,  Jong-Min Lee ,  Dong-Sik Lee

IPC: H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/31144

Abstract: A semiconductor device may include plugs disposed in a zigzag pattern, interconnections electrically connected to the plugs and a protection pattern which is interposed between the plugs and the interconnections to selectively expose the plugs. The interconnections may include a connection portion which is in contact with plugs selectively exposed by the protection pattern. A method of manufacturing a semiconductor device includes, after forming a molding pattern and a mask pattern, selectively etching a protection layer using the mask pattern to form a protection pattern exposing a plug.

Abstract translation: 半导体器件可以包括以锯齿形图案布置的插塞，电连接到插头的互连和插入在插头和互连之间的保护图案以选择性地暴露插头。 互连可以包括与由保护图案选择性地暴露的插头接触的连接部分。 制造半导体器件的方法包括：在形成模制图案和掩模图案之后，使用掩模图案选择性地蚀刻保护层以形成露出插头的保护图案。

公开(公告)号：US09761603B2

公开(公告)日：2017-09-12

申请号：US14964624

申请日：2015-12-10

Applicant: Min-Sung Song ,  Jae-Hwang Sim ,  Joon-Sung Lim

Inventor： Min-Sung Song ,  Jae-Hwang Sim ,  Joon-Sung Lim

IPC: H01L21/4763 ,  H01L27/11573 ,  H01L21/311 ,  H01L27/11526 ,  H01L21/033 ,  H01L21/768

CPC classification number: H01L27/11573 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L27/11526

Abstract: The inventive concepts provide methods for fabricating a semiconductor device and semiconductor devices fabricated by the same. According to the method, conductive lines having a fine pitch smaller than the minimum pitch realized by an exposure process may be formed using two or three photolithography processes and two spacer formation processes. In addition, node separation regions of the conductive lines may be easily formed without a misalignment problem.

公开(公告)号：US09041088B2

公开(公告)日：2015-05-26

申请号：US14339762

申请日：2014-07-24

Applicant: Jae-Hwang Sim ,  Jinhyun Shin ,  HoJun Seong

Inventor： Jae-Hwang Sim ,  Jinhyun Shin ,  HoJun Seong

IPC: H01L29/06 ,  H01L21/764 ,  H01L29/788 ,  H01L27/115 ,  H01L21/762

CPC classification number: H01L27/11521 ,  H01L21/76289 ,  H01L21/764 ,  H01L27/11517 ,  H01L27/11524 ,  H01L27/11563 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/7881

Abstract: Disclosed are non-volatile memory devices and methods of manufacturing the same. The non-volatile memory device includes device isolation patterns defining active portions in a substrate and gate structures disposed on the substrate. The active portions are spaced apart from each other in a first direction and extend in a second direction perpendicular to the first direction. The gate structures are spaced apart from each other in the second direction and extend in the first direction. Each of the device isolation patterns includes a first air gap, and each of a top surface and a bottom surface of the first air gap has a wave-shape in a cross-sectional view taken along the second direction.

Abstract translation: 公开了非易失性存储器件及其制造方法。 非易失性存储器件包括限定衬底中的有源部分和设置在衬底上的栅极结构的器件隔离图案。 有源部分在第一方向上彼此间隔开，并且在垂直于第一方向的第二方向上延伸。 栅极结构在第二方向上彼此间隔开并且在第一方向上延伸。 每个器件隔离图案包括第一气隙，并且第一气隙的顶表面和底表面中的每一个在沿着第二方向截取的截面图中具有波形。

公开(公告)号：US20150054176A1

公开(公告)日：2015-02-26

申请号：US14503498

申请日：2014-10-01

Applicant: Jae-Hwang Sim ,  Jinhyun Shin

Inventor： Jae-Hwang Sim ,  Jinhyun Shin

IPC: H01L21/3213 ,  H01L21/768

CPC classification number: H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L27/11519 ,  H01L27/11531

Abstract: Methods of fabricating semiconductor devices are provided including performing two photolithography processes and two spacer processes such that patterns are formed to have a pitch that is smaller than a limitation of photolithography process. Furthermore, line and pad portions are simultaneously defined by performing the photolithography process once and, thus, there is no necessity to perform an additional photolithography process for forming the pad portion. Related devices are also provided.

Abstract translation: 提供制造半导体器件的方法包括执行两个光刻工艺和两个间隔工艺，使得图案形成为具有小于光刻工艺限制的间距。 此外，通过执行一次光刻工艺同时限定线和焊盘部分，因此不需要执行用于形成焊盘部分的附加光刻工艺。 还提供了相关设备。

公开(公告)号：US08772855B2

公开(公告)日：2014-07-08

申请号：US12882436

申请日：2010-09-15

Applicant: Yoonmoon Park ,  Keonsoo Kim ,  Jinhyun Shin ,  Jae-Hwang Sim

Inventor： Yoonmoon Park ,  Keonsoo Kim ,  Jinhyun Shin ,  Jae-Hwang Sim

IPC: H01L29/788

CPC classification number: H01L27/11531 ,  H01L27/11526 ,  H01L28/20 ,  H01L28/24

Abstract: Embodiments of a semiconductor device including a resistor and a method of fabricating the same are provided. The semiconductor device includes a mold pattern disposed on a semiconductor substrate to define a trench, a resistance pattern including a body region and first and second contact regions, wherein the body region covers the bottom and sidewalls of the trench, the first and second contact regions extend from the extending from the body region over upper surfaces of the mold pattern, respectively; and first and second lines contacting the first and second contact regions, respectively.

Abstract translation: 提供了包括电阻器的半导体器件及其制造方法的实施例。 半导体器件包括设置在半导体衬底上以限定沟槽的模具图案，包括主体区域和第一和第二接触区域的电阻图案，其中主体区域覆盖沟槽的底部和侧壁，第一和第二接触区域 分别从模具图案的上表面上的身体区域延伸出来; 以及分别与第一和第二接触区域接触的第一和第二线路。

公开(公告)号：US08754464B2

公开(公告)日：2014-06-17

申请号：US13468552

申请日：2012-05-10

Applicant: Jae-Hwang Sim

Inventor： Jae-Hwang Sim

IPC: H01L29/76 ,  H01L29/792 ,  H01L29/788

CPC classification number: H01L21/28273 ,  H01L21/764 ,  H01L27/11529 ,  H01L29/42324 ,  H01L29/7881

Abstract: Non-volatile memory devices and methods of manufacturing the same are disclosed. In a non-volatile memory device, widths of a metal gate and an upper portion of a base gate in a gate electrode are less than the width of a hard mask pattern disposed on the metal gate. First and second protection spacers are disposed on opposing sidewalls of the metal gate and on opposing sidewalls of the upper portion of the base gate, respectively.

Abstract translation: 公开了非易失性存储器件及其制造方法。 在非易失性存储器件中，栅电极中的金属栅极和基极栅极的上部的宽度小于设置在金属栅极上的硬掩模图案的宽度。 第一和第二保护间隔物分别设置在金属栅极的相对的侧壁和基栅的上部的相对侧壁上。

公开(公告)号：US08697580B2

公开(公告)日：2014-04-15

申请号：US13678930

申请日：2012-11-16

Applicant: Young-Ho Lee ,  Jae-Hwang Sim ,  Sang-Yong Park ,  Kyung-Lyul Moon

Inventor： Young-Ho Lee ,  Jae-Hwang Sim ,  Sang-Yong Park ,  Kyung-Lyul Moon

IPC: H01L21/311

CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76229 ,  H01L21/76816 ,  H01L21/76838 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/11519 ,  H01L27/11526 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are included in the substrate. Both a blocking pattern covering a portion of the first layer in the first region and a low-density large-width pattern covering a portion of the first layer in the second region are simultaneously formed. A plurality of sacrificial mask patterns are formed on the first layer and the blocking pattern in the first region. A plurality of spacers covering exposed sidewalls of the plurality of sacrificial mask patterns are formed. The plurality of sacrificial mask patterns are removed. The first layer in the first and second regions are simultaneously etched by using the plurality of spacers and the blocking pattern as etch masks in the first region and using the low-density large-width pattern as an etch mask in the second region.

Abstract translation: 提供一种形成半导体器件的图案的方法，其中精细图案和大幅图案同时并且彼此相邻地形成。 在该方法中，在衬底上形成第一层以覆盖包括在衬底中的第一区域和第二区域。 同时形成覆盖第一区域中的第一层的一部分的阻挡图案和覆盖第二区域中的第一层的一部分的低密度大图案。 在第一层上形成多个牺牲掩模图案，并在第一区域中形成阻挡图案。 形成覆盖多个牺牲掩模图案的暴露侧壁的多个间隔物。 去除多个牺牲掩模图案。 通过使用多个间隔物和阻挡图案作为第一区域中的蚀刻掩模并且在第二区域中使用低密度大宽度图案作为蚀刻掩模，同时蚀刻第一和第二区域中的第一层。

公开(公告)号：US20140087555A1

公开(公告)日：2014-03-27

申请号：US14091680

申请日：2013-11-27

Applicant: Yoonmoon PARK ,  Jae-Hwang SIM ,  Se-Young PARK ,  Keonsoo KIM ,  Jaehan LEE ,  Seungwon SEONG

Inventor： Yoonmoon PARK ,  Jae-Hwang SIM ,  Se-Young PARK ,  Keonsoo KIM ,  Jaehan LEE ,  Seungwon SEONG

IPC: H01L21/768

CPC classification number: H01L27/3223 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76877 ,  H01L27/11519 ,  H01L27/11529 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate including a cell region and a core region adjacent to the cell region, active regions in the cell region and the core region, an interlayer insulating layer covering the active regions, upper cell contacts penetrating the interlayer insulating layer in the cell region, the upper cell contacts being adjacent to each other along a first direction and being electrically connected to the active regions, and core contacts penetrating the interlayer insulating layer in the active regions of the core region, the core contacts being adjacent to each other along the first direction and including upper connection core contacts electrically connected to the active regions, and dummy contacts adjacent to the upper connection core contacts, the dummy contacts being insulated from the active regions.

Abstract translation: 半导体器件包括：半导体衬底，包括单元区域和与单元区域相邻的芯区域，单元区域和芯区域中的有源区域，覆盖有源区域的层间绝缘层，穿过层间绝缘层的上部单元触点 电池区域，上电池触点沿着第一方向彼此相邻并且电连接到有源区域，并且芯触点穿透芯区域的有源区域中的层间绝缘层，芯触点与每个区域相邻 另一个沿着第一方向并且包括电连接到有源区的上连接芯触点，以及与上连接芯触点相邻的虚拟触头，虚拟触头与有源区绝缘。

公开(公告)号：US08519484B2

公开(公告)日：2013-08-27

申请号：US13368556

申请日：2012-02-08

Applicant: Dong-Won Kim ,  Jae-Hwang Sim ,  Keon-Soo Kim ,  Young-Ho Lee

Inventor： Dong-Won Kim ,  Jae-Hwang Sim ,  Keon-Soo Kim ,  Young-Ho Lee

IPC: H01L21/70

CPC classification number: H01L21/76229

Abstract: A semiconductor device having a dual trench and methods of fabricating the same, a semiconductor module, an electronic circuit board, and an electronic system are provided. The semiconductor device includes a semiconductor substrate having a cell region including a cell trench and a peripheral region including a peripheral trench. The cell trench is filled with a core insulating material layer, and the peripheral trench is filled with a padding insulating material layer conformably formed on an inner surface thereof and a core insulating material layer formed on an inner surface of the padding insulating material layer. The core insulating material layer has a greater fluidity than the padding insulating material layer.

Abstract translation: 提供具有双沟槽的半导体器件及其制造方法，半导体模块，电子电路板和电子系统。 半导体器件包括具有包括单元沟道的单元区域和包括外围沟槽的周边区域的半导体衬底。 电池沟槽填充有芯绝缘材料层，并且周边沟槽填充有在内表面上顺应地形成的填充绝缘材料层和形成在填充绝缘材料层的内表面上的芯绝缘材料层。 芯绝缘材料层具有比填充绝缘材料层更大的流动性。

公开(公告)号：US20120299077A1

公开(公告)日：2012-11-29

申请号：US13412863

申请日：2012-03-06

Applicant: Jae-Hwang SIM ,  Jae-Bok Baek

Inventor： Jae-Hwang SIM ,  Jae-Bok Baek

IPC: H01L29/78 ,  H01L27/088

CPC classification number: H01L21/28 ,  H01L21/28273 ,  H01L21/764 ,  H01L27/11529 ,  H01L27/11546 ,  H01L29/7881

Abstract: A semiconductor device includes a substrate including a first region and a second region, a gate group disposed in the first region of the substrate, the gate group including a plurality of cell gate patterns and at least one selection gate pattern, a first gate pattern disposed in the second region of the substrate, a group spacer covering a top surface and a side surface of the gate group, the group spacer having a first inflection point, and a first pattern spacer covering a top surface and a side surface of the first gate pattern, the first pattern spacer having a second inflection point.

Abstract translation: 半导体器件包括：衬底，包括第一区域和第二区域;栅极组，设置在衬底的第一区域中，栅极组包括多个单元栅极图案和至少一个选择栅极图案，第一栅极图案布置 在衬底的第二区域中，覆盖栅极组的顶表面和侧表面的组间隔件，具有第一拐点的组间隔件和覆盖第一栅极的顶表面和侧表面的第一图案间隔件 第一图案间隔物具有第二拐点。