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    Reliable high voltage gate dielectric layers using a dual nitridation process
    35.
    发明申请
    Reliable high voltage gate dielectric layers using a dual nitridation process 有权
    使用双重氮化工艺的可靠的高压栅极电介质层

    公开(公告)号：US20070117331A1

    公开(公告)日：2007-05-24

    申请号：US11626624

    申请日：2007-01-24

    Applicant: Rajesh Khamankar ,  Douglas Grider ,  Hiroaki Niimi ,  April Gurba ,  Toan Tran ,  James Chambers

    Inventor： Rajesh Khamankar ,  Douglas Grider ,  Hiroaki Niimi ,  April Gurba ,  Toan Tran ,  James Chambers

    IPC: H01L21/336 ,  H01L29/76

    CPC classification number: H01L21/823462 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3144 ,  H01L29/518

    Abstract: Dual gate dielectric layers are formed on a semiconductor substrate for MOS transistor fabrication. A first dielectric layer (30) is formed on a semiconductor substrate (10). A first plasma nitridation process is performed on said first dielectric layer. The first dielectric layer (30) is removed in regions of the substrate and a second dielectric layer (50) is formed in these regions. A second plasma nitridation process is performed on the first dielectric layer and the second dielectric. MOS transistors (160, 170) are then fabricated using the dielectric layers (30, 50).

    Abstract translation: 在用于MOS晶体管制造的半导体衬底上形成双栅介质层。 第一电介质层（30）形成在半导体衬底（10）上。 在所述第一介电层上进行第一等离子体氮化处理。 在衬底的区域中去除第一电介质层（30），并且在这些区域中形成第二电介质层（50）。 在第一电介质层和第二电介质上进行第二等离子体氮化处理。 然后使用电介质层（30,50）制造MOS晶体管（160,170）。

    REFRACTORY METAL-BASED ELECTRODES FOR WORK FUNCTION SETTING IN SEMICONDUCTOR DEVICES
    38.
    发明申请
    REFRACTORY METAL-BASED ELECTRODES FOR WORK FUNCTION SETTING IN SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20060273414A1

    公开(公告)日：2006-12-07

    申请号：US11465219

    申请日：2006-08-17

    Applicant: Luigi Colombo ,  James Chambers ,  Mark Visokay

    Inventor： Luigi Colombo ,  James Chambers ,  Mark Visokay

    IPC: H01L29/94

    CPC classification number: H01L21/823842 ,  H01L29/4958

    Abstract: The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate dielectric includes a refractory metal and is located over a semiconductor substrate (115). The semiconductor substrate has a conduction band and a valence band. The gate is located over the gate dielectric and includes the refractory metal. The gate has a work function aligned toward the conduction band or the valence band. Other embodiments include an alternative gate structure (200), a method of forming a gate structure (300) for a semiconductor device (301) and a dual gate integrated circuit (400).

    Semiconductor CMOS devices and methods with NMOS high-k dielectric formed prior to core PMOS dielectric formation
    39.
    发明申请
    Semiconductor CMOS devices and methods with NMOS high-k dielectric formed prior to core PMOS dielectric formation 有权
    半导体CMOS器件和方法，在核心PMOS电介质形成之前形成NMOS高k电介质

    公开(公告)号：US20060246716A1

    公开(公告)日：2006-11-02

    申请号：US11118237

    申请日：2005-04-29

    Applicant: Luigi Colombo ,  James Chambers ,  Mark Visokay

    Inventor： Luigi Colombo ,  James Chambers ,  Mark Visokay

    IPC: H01L21/4763

    CPC classification number: H01L21/823857 ,  H01L27/11

    Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. A first oxide layer is formed in core and I/O regions of a semiconductor device (506). The first oxide layer is removed (508) from the core region of the device. A high-k dielectric layer is formed (510) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions of the core and I/O regions. A second oxide layer is formed (516) within NMOS regions of the core and I/O regions and a nitridation process is performed (518) that nitrides the second oxide layer and the high-k dielectric layer.

    Abstract translation: 本发明通过提供在NMOS区内选择性地形成高k电介质层的制造方法来促进半导体制造。 在半导体器件（506）的芯和I / O区域中形成第一氧化物层。 第一氧化物层从器件的核心区域移除（508）。 在芯和I / O区域上形成高k电介质层（510）。 然后，从芯和I / O区域的PMOS区域去除高k电介质层（512）。 在芯和I / O区域的NMOS区域内形成第二氧化物层（516），并且执行氮化处理（518），其氮化第二氧化物层和高k电介质层。

    Active/passive seal rotating control head
    40.
    发明授权
    Active/passive seal rotating control head 有权
    主动/被动密封旋转控制头

    公开(公告)号：US07040394B2

    公开(公告)日：2006-05-09

    申请号：US10285336

    申请日：2002-10-31

    Applicant: Thomas F. Bailey ,  James Chambers ,  Don M. Hannegan

    Inventor： Thomas F. Bailey ,  James Chambers ,  Don M. Hannegan

    IPC: E21B33/068

    CPC classification number: E21B33/085

    Abstract: The present invention generally relates to an apparatus and method for sealing a tubular string. In one aspect, a drilling system is provided. The drilling system includes a rotating control head for sealing the tubular string while permitting axial movement of the string relative to the rotating control head. The drilling system also includes an actuating fluid for actuating the rotating control head and maintaining a pressure differential between a fluid pressure in the rotating control head and a wellbore pressure. Additionally, the drilling system includes a cooling medium for passing through the rotating control head. In another aspect, a rotating control head is provided. In yet another aspect, a method for sealing a tubular in a rotating control head is provided.

    Abstract translation: 本发明一般涉及用于密封管状管柱的装置和方法。 一方面，提供一种钻井系统。 钻井系统包括用于密封管柱的旋转控制头，同时允许绳相对于旋转控制头的轴向移动。 钻井系统还包括用于致动旋转控制头并且保持旋转控制头中的流体压力与井筒压力之间的压力差的致动流体。 此外，钻井系统包括用于通过旋转控制头的冷却介质。 另一方面，提供一种旋转控制头。 另一方面，提供一种用于密封旋转控制头中的管状物的方法。

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