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    WORK FUNCTION CONTROL OF METALS
    2.
    发明申请
    WORK FUNCTION CONTROL OF METALS 有权
    金属的工作功能控制

    公开(公告)号：US20080044957A1

    公开(公告)日：2008-02-21

    申请号：US11870631

    申请日：2007-10-11

    申请人： James Chambers ,  Mark Visokay ,  Luigi Colombo ,  Antonio Rotondaro

    发明人： James Chambers ,  Mark Visokay ,  Luigi Colombo ,  Antonio Rotondaro

    IPC分类号： H01L21/84

    CPC分类号： H01L21/823842

    摘要： Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal, which is a ‘mid gap’ metal, is manipulated in first and second regions by second and third metals, respectively, to move the work function of the first metal in opposite directions in the different regions. The resulting work functions in the different regions correspond to that of different types of the transistors that are to be formed.

    摘要翻译： 公开了具有不同功函数的金属栅极晶体管。 在一个示例中，第一金属是“中间间隙”金属，分别在第一和第二区域中被第二和第三金属操纵，以在不同区域中沿相反方向移动第一金属的功函数。 在不同区域中产生的功函数对应于将要形成的不同类型的晶体管。

    Semiconductor CMOS Devices and Methods with NMOS High-K Dielectric Present in Core Region that Mitigate Damage to Dielectric Materials
    3.
    发明申请
    Semiconductor CMOS Devices and Methods with NMOS High-K Dielectric Present in Core Region that Mitigate Damage to Dielectric Materials 有权
    半导体CMOS器件和方法与NMOS High-K介质存在于核心区域，减轻对介质材料的损害

    公开(公告)号：US20070122962A1

    公开(公告)日：2007-05-31

    申请号：US11620447

    申请日：2007-01-05

    申请人： James Chambers ,  Mark Visokay ,  Luigi Colombo

    发明人： James Chambers ,  Mark Visokay ,  Luigi Colombo

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823857 ,  H01L21/823842 ,  Y10S438/981

    摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An I/O dielectric layer is formed in core and I/O regions of a semiconductor device (506). The I/O dielectric layer is removed (508) from the core region of the device. A core dielectric layer is formed in the core region (510). A barrier layer is deposited and patterned to expose the NMOS devices of the core region (512). The core dielectric layer is removed from the core NMOS devices (514). A high-k dielectric layer is formed (514) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions/devices of the core region and the NMOS and PMOS regions/devices of the I/O region.

    摘要翻译： 本发明通过提供在NMOS区内选择性地形成高k电介质层的制造方法来促进半导体制造。 在半导体器件（506）的芯和I / O区域中形成I / O电介质层。 从器件的芯区域去除（508）I / O电介质层。 在芯区域（510）中形成芯介质层。 屏蔽层被沉积并图案化以暴露核心区域（512）的NMOS器件。 从核心NMOS器件（514）去除芯介质层。 在核心和I / O区域上形成高k电介质层（514）。 然后，从核心区域的PMOS区域/器件和I / O区域的NMOS和PMOS区域/器件去除高k电介质层（512）。

    Process for manufacturing dual work function metal gates in a microelectronics device
    4.
    发明申请
    Process for manufacturing dual work function metal gates in a microelectronics device 有权

    公开(公告)号：US20070037343A1

    公开(公告)日：2007-02-15

    申请号：US11200741

    申请日：2005-08-10

    申请人： Luigi Colombo ,  James Chambers ,  Mark Visokay

    发明人： Luigi Colombo ,  James Chambers ,  Mark Visokay

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823842 ,  H01L29/66545

    摘要： The present invention provides a method of forming a dual work function metal gate microelectronics device 200. In one aspect, the method includes forming nMOS and pMOS stacked gate structures 315a and 315b. The nMOS and pMOS stacked gate structures 315a and 315b each comprise a gate dielectric 205, a first metal layer, 305 located over the gate dielectric 205 and a sacrificial gate layer 310 located over the first metal layer 305. The method further includes removing the sacrificial gate layer 310 in at least one of the nMOS or pMOS stacked gate structures, thereby forming a gate opening 825 and modifying the first metal layer 305 within the gate opening 825 to form a gate electrode with a desired work function.

    Anneal of high-k dielectric using NH3 and an oxidizer
    5.
    发明申请
    Anneal of high-k dielectric using NH3 and an oxidizer 审中-公开
    使用NH3和氧化剂的高k电介质的退火

    公开(公告)号：US20050124121A1

    公开(公告)日：2005-06-09

    申请号：US10731647

    申请日：2003-12-09

    申请人： Antonio Rotondaro ,  James Chambers ,  Mark Visokay ,  Luigi Colombo

    发明人： Antonio Rotondaro ,  James Chambers ,  Mark Visokay ,  Luigi Colombo

    IPC分类号： C23C16/56 ,  H01L21/28 ,  H01L21/31 ,  H01L21/314 ,  H01L21/316 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/8242 ,  H01L29/51

    CPC分类号： H01L21/02318 ,  C23C16/56 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/3143 ,  H01L21/31641 ,  H01L21/31645 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

    摘要： The present invention pertains to annealing a high dielectric constant (high-k) material in a manner that substantially reduces or eliminates disadvantages and problems heretofore associated with the same. In particular, the high-k material is annealed in an ambient having a single chemistry of nitrogen and hydrogen, such as ammonia (NH3), to nitride and react unwanted impurities, and an oxidizer to oxidize and densify the high-k material, while mitigating growth of a lower-k material at an interface of the high-k material and an underlying substrate. Additionally, particular temperatures and pressures are utilized within the process so that the risk of an undesired exothermic reaction is mitigated. Annealing the high-k material in accordance with manners disclosed herein has application to semiconductor fabrication processes and, as such, is discussed herein within the context of the same.

    摘要翻译： 本发明涉及以大大减少或消除与之相关的缺点和问题的方式退火高介电常数（高k）材料。 特别地，高k材料在具有氮和氢的单一化学性质（例如氨（NH 3））的环境中退火至氮化物并反应不需要的杂质，以及氧化剂氧化和 致密化高k材料，同时减轻在高k材料和下层衬底的界面处的较低k材料的生长。 此外，在该方法中利用特定的温度和压力，以便减轻不期望的放热反应的风险。 根据本文公开的方式对高k材料进行退火，已经应用于半导体制造工艺，并且因此本文在其上下文中讨论。

    Refractory metal-based electrodes for work function setting in semiconductor devices
    8.
    发明申请
    Refractory metal-based electrodes for work function setting in semiconductor devices 有权
    用于半导体器件功能设置的耐火金属基电极

    公开(公告)号：US20050258500A1

    公开(公告)日：2005-11-24

    申请号：US10852523

    申请日：2004-05-24

    申请人： Luigi Colombo ,  James Chambers ,  Mark Visokay

    发明人： Luigi Colombo ,  James Chambers ,  Mark Visokay

    IPC分类号： H01L21/3205 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/76 ,  H01L29/78

    CPC分类号： H01L21/823842 ,  H01L29/4958

    摘要： The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate dielectric includes a refractory metal and is located over a semiconductor substrate (115). The semiconductor substrate has a conduction band and a valence band. The gate is located over the gate dielectric and includes the refractory metal. The gate has a work function aligned toward the conduction band or the valence band. Other embodiments include an alternative gate structure (200), a method of forming a gate structure (300) for a semiconductor device (301) and a dual gate integrated circuit (400).

    摘要翻译： 本发明在一个实施例中提供一种栅极结构（100）。 栅极结构包括栅极电介质（105）和栅极（110）。 栅极电介质包括难熔金属并且位于半导体衬底（115）之上。 半导体衬底具有导带和价带。 栅极位于栅极电介质上方并且包括难熔金属。 栅极具有与导带或价带对准的功函数。 其他实施例包括替代栅极结构（200），形成用于半导体器件（301）的栅极结构（300）和双栅极集成电路（400）的方法。

    Dual work function metal gate integration in semiconductor devices
    9.
    发明申请
    Dual work function metal gate integration in semiconductor devices 有权
    双功能金属门集成在半导体器件中

    公开(公告)号：US20050258468A1

    公开(公告)日：2005-11-24

    申请号：US10890365

    申请日：2004-07-13

    申请人： Luigi Colombo ,  James Chambers ,  Mark Visokay

    发明人： Luigi Colombo ,  James Chambers ,  Mark Visokay

    IPC分类号： H01L21/3205 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/76 ,  H01L29/78

    CPC分类号： H01L21/823842 ,  H01L29/4958

    摘要： The present invention provides, in one embodiment, a process for forming a dual work function metal gate semiconductor device (100). The process includes providing a semiconductor substrate (105) having a gate dielectric layer (110) thereon and a metal layer (205) on the gate dielectric layer. A work function of the metal layer is matched to a conduction band or a valence band of the semiconductor substrate. The process also includes forming a conductive barrier layer (210) on a portion (215) of the metal layer and a material layer (305) on the metal layer. The metal layer and the material layer are annealed to form a metal alloy layer (405) to thereby match a work function of the metal alloy layer to another of the conduction band or the valence band of the substrate. Other embodiments of the invention include a dual work function metal gate semiconductor device (900) and an integrated circuit (1000).

    摘要翻译： 本发明在一个实施例中提供了一种用于形成双功函数金属栅极半导体器件（100）的工艺。 该方法包括提供其上具有栅极电介质层（110）的半导体衬底（105）和栅极电介质层上的金属层（205）。 金属层的功函数与半导体衬底的导带或价带相匹配。 该方法还包括在金属层的一部分（215）和金属层上的材料层（305）上形成导电阻挡层（210）。 对金属层和材料层进行退火以形成金属合金层（405），从而将金属合金层的功函数与衬底的导带或价带中的另一个相匹配。 本发明的其它实施例包括双功函数金属栅极半导体器件（900）和集成电路（1000）。

    Metal gate MOS transistors and methods for making the same
    10.
    发明申请
    Metal gate MOS transistors and methods for making the same 有权
    金属栅极MOS晶体管及其制造方法

    公开(公告)号：US20050059198A1

    公开(公告)日：2005-03-17

    申请号：US10661130

    申请日：2003-09-12

    申请人： Mark Visokay ,  Luigi Colombo ,  James Chambers

    发明人： Mark Visokay ,  Luigi Colombo ,  James Chambers

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L21/44 ,  H01L29/76

    CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665

    摘要： Semiconductor devices and fabrication methods are provided, in which metal transistor gates are provided for MOS transistors. Metal boride is formed above a gate dielectric to create PMOS gate structures and metal nitride is formed over a gate dielectric to provide NMOS gate structures. The metal portions of the gate structures are formed from an initial starting material that is either a metal boride or a metal nitride, after which the starting material is provided with boron or nitrogen in one of the PMOS and NMOS regions through implantation, diffusion, or other techniques, either before or after formation of the conductive upper material, and before or after gate patterning. The change in the boron or nitrogen content of the starting material provides adjustment of the material work function, thereby tuning the threshold voltage of the resulting PMOS or NMOS transistors.

    摘要翻译： 提供了半导体器件和制造方法，其中为MOS晶体管提供金属晶体管栅极。 金属硼化物形成在栅极电介质上方以产生PMOS栅极结构，并且在栅极电介质上形成金属氮化物以提供NMOS栅极结构。 栅极结构的金属部分由起始原料是金属硼化物或金属氮化物形成，之后起始材料通过注入，扩散或扩散形成在PMOS和NMOS区域之一中的硼或氮中。 在形成导电上部材料之前或之后以及栅极图案化之前或之后的其它技术。 起始材料的硼或氮含量的变化提供材料功函数的调整，从而调谐所得PMOS或NMOS晶体管的阈值电压。