公开(公告)号：US08350608B2

公开(公告)日：2013-01-08

申请号：US12976449

申请日：2010-12-22

申请人： Hui Dong Lee ,  Seok Ju Yun ,  Kwi Dong Kim ,  Jong-Kee Kwon ,  Sang-Hyun Cho

发明人： Hui Dong Lee ,  Seok Ju Yun ,  Kwi Dong Kim ,  Jong-Kee Kwon ,  Sang-Hyun Cho

IPC分类号： H03L7/06

CPC分类号： H03L7/083 ,  H03J2200/10 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/187

摘要： Provided is a PLL circuit including automatic frequency control circuit and an operating method thereof. The voltage controlled oscillator is primarily controlled by an automatic frequency control circuit, and is secondarily controlled by a loop filter. The voltage controlled oscillator outputs a coarsely-tuned oscillation signal when primarily controlled, and outputs a finely-tuned oscillation signal when secondarily controlled. The PLL circuit can have a quick frequency fixing time, and output the oscillation signal having a broad and stable frequency. Moreover, the noise characteristic of the PLL circuit is enhanced.

摘要翻译： 提供一种包括自动频率控制电路的PLL电路及其操作方法。 压控振荡器主要由自动频率控制电路控制，二次由环路滤波器控制。 压控振荡器在主要受控时输出粗调谐振荡信号，并在二次控制时输出微调振荡信号。 PLL电路可以具有快速的频率固定时间，并输出具有宽而稳定频率的振荡信号。 此外，提高了PLL电路的噪声特性。

公开(公告)号：US20120226831A1

公开(公告)日：2012-09-06

申请号：US13471236

申请日：2012-05-14

申请人： Ik Jae CHUN ,  Chun Gi Lyuh ,  Se Wan Heo ,  Sang Hun Yoon ,  Tae Moon Roh ,  Jong Kee Kwon ,  Jong Dae Kim

发明人： Ik Jae CHUN ,  Chun Gi Lyuh ,  Se Wan Heo ,  Sang Hun Yoon ,  Tae Moon Roh ,  Jong Kee Kwon ,  Jong Dae Kim

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： Provided are a memory system and an integrated management method for a plurality of direct memory access (DMA) channels. The memory system includes a memory controller exchanging data with a memory and having a plurality of channels physically separated from each other, and a DMA controller having a plurality of DMA channels physically separated from each other and in contact with the plurality of channels of the memory controller, and exchanging data with the memory via the plurality of DMA channels and the memory controller.

摘要翻译： 提供了用于多个直接存储器访问（DMA）通道的存储器系统和集成管理方法。 存储器系统包括存储器控制器，其与存储器交换数据并且具有物理上彼此分离的多个通道;以及DMA控制器，其具有彼此物理上彼此分离并与存储器的多个通道接触的多个DMA通道 控制器，并且经由多个DMA通道和存储器控制器与存储器交换数据。

公开(公告)号：US20120154028A1

公开(公告)日：2012-06-21

申请号：US13243955

申请日：2011-09-23

申请人： Yi-Gyeong Kim ,  Bong Chan Kim ,  Min-Hyung Cho ,  Jong-Kee Kwon

发明人： Yi-Gyeong Kim ,  Bong Chan Kim ,  Min-Hyung Cho ,  Jong-Kee Kwon

IPC分类号： G05F1/10

CPC分类号： H03F3/45475 ,  H03F2203/45248 ,  H03F2203/45514 ,  H03F2203/45541 ,  H03F2203/45551

摘要： Disclosed is a bias circuit which includes a bias voltage generating part configured to generate a bias voltage using a reference current and a variable current; a reference current source part configured to provide the reference current to the bias voltage generating part; and a current adjusting part configured to provide the variable current to the bias voltage generating part and to adjust the amount of the variable current according to voltage levels of at least two input signals. The bias circuit prevents an increase in power consumption and improves a slew rate at the same time.

摘要翻译： 公开了一种偏置电路，其包括被配置为使用参考电流和可变电流产生偏置电压的偏置电压产生部件; 参考电流源部，被配置为将所述参考电流提供给所述偏置电压产生部; 以及电流调节部，被配置为向所述偏置电压生成部提供所述可变电流，并且根据至少两个输入信号的电压电平来调整所述可变电流的量。 偏置电路可以防止功耗的增加，同时提高转换速率。

公开(公告)号：US20120146830A1

公开(公告)日：2012-06-14

申请号：US13243267

申请日：2011-09-23

申请人： Young-deuk JEON ,  Young Kyun CHO ,  Jaewon NAM ,  Jong-Kee KWON

发明人： Young-deuk JEON ,  Young Kyun CHO ,  Jaewon NAM ,  Jong-Kee KWON

IPC分类号： H03M1/12

CPC分类号： H03M1/164 ,  H03M1/468

摘要： Provided is an analog digital converter (ADC). The ADC includes: a capacitor array generating a level voltage; a comparator outputting a compare signal by comparing the level voltage; and a logic circuit determining digital bits of an analog signal based on the compare signal, wherein the logic circuit determines at least one digital bit among digital bits of the analog signal while a sampling operation of the analog signal is performed in the capacitor array.

摘要翻译： 提供了一种模拟数字转换器（ADC）。 ADC包括：产生电平电压的电容器阵列; 比较器，通过比较电平电压输出比较信号; 以及逻辑电路，其基于所述比较信号确定模拟信号的数字位，其中所述逻辑电路在所述电容器阵列中执行所述模拟信号的采样操作时，确定所述模拟信号的数字位中的至少一个数字位。

公开(公告)号：US07977979B2

公开(公告)日：2011-07-12

申请号：US12507357

申请日：2009-07-22

申请人： Young Kyun Cho ,  Young Deuk Jeon ,  Jae Won Nam ,  Jong Kee Kwon

发明人： Young Kyun Cho ,  Young Deuk Jeon ,  Jae Won Nam ,  Jong Kee Kwon

IPC分类号： H03K5/22

CPC分类号： H03F3/45475 ,  H03F3/45968 ,  H03F2203/45212

摘要： A high-speed multi-stage voltage comparator is provided. The multi-stage voltage comparator is configured to eliminate offset from outputs of preamplifiers through respective offset-cancellation switches, and to reset the outputs of the preamplifiers through respective reset switches to reduce an output recovery time. Thus, the multi-stage voltage comparator operates with high accuracy and at a high speed, so that it can be usefully applied to an analog-to-digital converter (ADC), and particularly, a high-speed successive approximation register ADC (SAR ADC).

摘要翻译： 提供了一个高速多级电压比较器。 多级电压比较器被配置为消除通过相应的偏移消除开关的前置放大器的输出的偏移，并且通过相应的复位开关复位前置放大器的输出以减少输出恢复时间。 因此，多级电压比较器以高精度和高速运行，从而可以有效地应用于模数转换器（ADC），特别是高速逐次逼近寄存器ADC（SAR） ADC）。

公开(公告)号：US20110142345A1

公开(公告)日：2011-06-16

申请号：US12783180

申请日：2010-05-19

申请人： Sang Hun Yoon ,  Ik Jae Chun ,  Chun Gi Lyuh ,  Jung Hee Suk ,  Tae Moon Roh ,  Jong Kee Kwon ,  Jong Dae Kim

发明人： Sang Hun Yoon ,  Ik Jae Chun ,  Chun Gi Lyuh ,  Jung Hee Suk ,  Tae Moon Roh ,  Jong Kee Kwon ,  Jong Dae Kim

IPC分类号： G06K9/46

CPC分类号： G06K9/4614

摘要： Provided are an apparatus and method for recognizing an image. In the apparatus and method for recognizing an image, various features can be extracted by a Haar-like filter using 1st to nth order gradients of the x- and y-axis of an input image, and the input image is correctly classified as a true or false image using, in stages, the extracted features of the input image, multiple threshold values for a true image and multiple threshold values for a false image. Accordingly, the apparatus and method achieve a high recognition rate by performing a small amount of computation. Consequently, it is possible to rapidly and correctly recognize an image, enabling real-time image recognition.

摘要翻译： 提供了一种用于识别图像的装置和方法。 在用于识别图像的装置和方法中，可以通过输入图像的x轴和y轴的第1至n阶梯度的Haar样滤波器提取各种特征，并且输入图像被正确地分类为真 或分别使用输入图像的提取特征，用于真实图像的多个阈值和用于假图像的多个阈值的假图像。 因此，该装置和方法通过执行少量的计算来实现高识别率。 因此，可以快速且正确地识别图像，从而实现图像识别。

公开(公告)号：US07928806B2

公开(公告)日：2011-04-19

申请号：US12561910

申请日：2009-09-17

申请人： Hui Dong Lee ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Pil Hong ,  Sang Gug Lee

发明人： Hui Dong Lee ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Pil Hong ,  Sang Gug Lee

IPC分类号： H03B5/12 ,  H03L5/00 ,  H03L7/06 ,  H03L7/08 ,  H03L7/085 ,  H03L7/089 ,  H03L7/099 ,  H03L7/18

CPC分类号： H03L7/0891 ,  H03L5/00 ,  H03L7/099

摘要： Provided is a low voltage frequency synthesizer using a boosting method for a power supply voltage of a charge pump. The low voltage frequency synthesizer includes a phase/frequency detector (PFD) that receives and compares a reference frequency and a feedback frequency to output a comparison signal, a charge pump that receives the comparison signal to output a current corresponding to the comparison signal, a low-pass filter (LPF) that generates a voltage corresponding to the output current of the charge pump, a voltage controlled oscillator (VCO) that receives the voltage of the LPF, amplifies the voltage to generate a boosting voltage, and outputs a frequency corresponding to the received voltage, and a DC converter that receives the boosting voltage of the VCO, converts the boosting voltage into a DC voltage, and applies the DC voltage as a power supply voltage of the charge pump. Since the supply voltage of the charge pump is provided from the LC-circuit-based VCO, the frequency synthesizer has superior characteristics such as a wide locking range, low phase noise, and the prevention of performance degradation caused by an external environment or process variations.

摘要翻译： 提供了使用电荷泵的电源电压的升压方法的低压频率合成器。 所述低电压频率合成器包括接收比较参考频率和反馈频率以输出比较信号的相位/频率检测器（PFD），接收比较信号以输出与比较信号相对应的电流的电荷泵， 产生与电荷泵的输出电流相对应的电压的低通滤波器（LPF），接收LPF电压的压控振荡器（VCO），放大电压以产生升压电压，并输出对应的频率 以及接收VCO的升压电压的DC转换器，将升压电压转换成直流电压，并施加直流电压作为电荷泵的电源电压。 由于电荷泵的电源电压是从基于LC电路的VCO提供的，因此频率合成器具有优异的特性，例如宽锁定范围，低相位噪声，以及防止由外部环境或工艺变化引起的性能下降 。

公开(公告)号：US20110022647A1

公开(公告)日：2011-01-27

申请号：US12843550

申请日：2010-07-26

申请人： Chun Gi LYUH ,  Ik Jae Chun ,  Jung Hee Suk ,  Tae Moon Roh ,  Jong Kee Kwon ,  Jong Dae Kim

发明人： Chun Gi LYUH ,  Ik Jae Chun ,  Jung Hee Suk ,  Tae Moon Roh ,  Jong Kee Kwon ,  Jong Dae Kim

IPC分类号： G06F7/485

CPC分类号： G06F7/544

摘要： Provided is an apparatus for calculating an absolute difference capable of efficiently performing an absolute difference using an adder. The apparatus for calculating an absolute difference includes a comparator comparing values of two integers, first and second selectors each selecting and outputting one of the two integers according to the comparison results of the comparator, an inverter complementing the result value selected by the second selector; and an adder adding up the result value selected by the first selector, the value complemented by the inverter, and 1.

摘要翻译： 提供了一种用于计算能够使用加法器有效地执行绝对差的绝对差的装置。 用于计算绝对差的装置包括比较器，比较器比较两个整数的值，第一和第二选择器，每个选择器根据比较器的比较结果选择和输出两个整数中的一个;逆变器，补偿由第二选择器选择的结果值; 和加法器将由第一选择器选择的结果值相加，由逆变器补充的值，以及1。

公开(公告)号：US07847713B2

公开(公告)日：2010-12-07

申请号：US12433780

申请日：2009-04-30

申请人： Jae Won Nam ,  Young Deuk Jeon ,  Young Kyun Cho ,  Jong Kee Kwon

发明人： Jae Won Nam ,  Young Deuk Jeon ,  Young Kyun Cho ,  Jong Kee Kwon

IPC分类号： H03M1/10

CPC分类号： H03M1/162

摘要： Provided is an algorithmic analog-to-digital converter (ADC). In the algorithmic ADC, the number of preprocessing amplifiers used in a flash ADC is reduced by sharing the preprocessing amplifiers in the flash ADC, and thus chip size can be reduced. In addition, power consumption can be reduced by dynamically decreasing the bandwidth of an operational amplifier included in a multiplying digital-to-analog converter (MDAC) according to a required resolution.

摘要翻译： 提供了一种算法模数转换器（ADC）。 在算法ADC中，通过在闪存ADC中共享预处理放大器来减少闪存ADC中使用的预处理放大器的数量，从而可以减少芯片尺寸。 此外，可以通过根据所需分辨率动态地减小包括在乘法数模转换器（MDAC）中的运算放大器的带宽来降低功耗。

公开(公告)号：US20100156692A1

公开(公告)日：2010-06-24

申请号：US12539406

申请日：2009-08-11

申请人： Young Deuk JEON ,  Young Kyun Cho ,  Jae Won Nam ,  Jong Kee Kwon

发明人： Young Deuk JEON ,  Young Kyun Cho ,  Jae Won Nam ,  Jong Kee Kwon

IPC分类号： H03M1/34 ,  H03M1/12

CPC分类号： H03M1/164 ,  H03M1/1215 ,  H03M1/468 ,  H03M1/804

摘要： A multi-stage dual successive approximation register analog-to-digital converter (SAR ADC) and a method of performing analog-to-digital conversion using the same are provided. The multi-stage dual SAR ADC includes: a plurality of SAR ADC stages for converting an analog input voltage into a predetermined bit digital signal, each SAR ADC stage being serially connected to one another and including two SAR ADCs; and at least one residue amplifier respectively connected between every two successive SAR ADC stages, amplifying residue voltage output from a previous SAR ADC stage to output the amplified residue voltage to a next SAR ADC stage. The two SAR ADCs of the previous SAR ADC stage share the residue amplifier.

摘要翻译： 提供了多级双逐次逼近寄存器模数转换器（SAR ADC）和使用其进行模数转换的方法。 多级双SAR ADC包括：多个SAR ADC级，用于将模拟输入电压转换为预定位数字信号，每个SAR ADC级串联连接并包括两个SAR ADC; 和分别连接在每两个连续的SAR ADC级之间的至少一个残余放大器，放大从先前的SAR ADC级输出的剩余电压，以将放大的残余电压输出到下一个SAR ADC级。 前一个SAR ADC级的两个SAR ADC共享残留放大器。