Metal-filled openings for submicron devices and methods of manufacture thereof
    31.
    发明申请
    Metal-filled openings for submicron devices and methods of manufacture thereof 有权
    用于亚微米器件的金属填充开口及其制造方法

    公开(公告)号:US20050275941A1

    公开(公告)日:2005-12-15

    申请号:US10854061

    申请日:2004-05-26

    CPC分类号: H01L21/7684 H01L21/76877

    摘要: A method of forming a metal-filled opening in a semiconductor or other submicron device substrate includes forming a conductive bulk layer over the substrate surface and in the opening, wherein the conductive bulk layer has a first grain size. A conductive cap layer is formed over the conductive bulk layer, the conductive cap layer having a second grain size that is substantially smaller than the first grain size. At least one of the conductive bulk and cap layers are then planarized to form a planar surface that is substantially coincident with the substrate surface.

    摘要翻译: 在半导体或其他亚微米器件衬底中形成填充金属的开口的方法包括在衬底表面和开口中形成导电体层,其中导电体层具有第一晶粒尺寸。 导电盖层形成在导电体层之上,导电盖层具有基本上小于第一晶粒尺寸的第二晶粒尺寸。 导电体和盖层中的至少一个然后被平坦化以形成基本上与衬底表面重合的平坦表面。

    Novel method to reduce Rs pattern dependence effect
    32.
    发明申请
    Novel method to reduce Rs pattern dependence effect 有权
    降低Rs模式依赖效应的新方法

    公开(公告)号:US20050085066A1

    公开(公告)日:2005-04-21

    申请号:US10687183

    申请日:2003-10-16

    摘要: A method of forming a copper interconnect in an opening within a pattern is described. The copper interconnect has an Rs that is nearly independent of opening width and pattern density. A first copper layer having a concave upper surface and thickness t1 is formed in a via or trench in a dielectric layer by depositing copper and performing a first CMP step. A second copper layer with a thickness t2 where t2≦t1 and having a convex lower surface is deposited on the first copper layer by a selective electroplating method. The first and second copper layers are annealed and then a second CMP step planarizes the second copper layer to become coplanar with the dielectric layer. The invention is also a copper interconnect comprised of the aforementioned copper layers where the first copper layer has a grain density (GD1)≧GD2 for the second copper layer.

    摘要翻译: 描述了在图案内的开口中形成铜互连的方法。 铜互连具有几乎独立于开口宽度和图案密度的Rs。 通过沉积铜并执行第一CMP步骤,在电介质层中的通孔或沟槽中形成具有凹上表面和厚度t 1的第一铜层。 具有厚度为2 的第二铜层,其中具有凸下表面的第二铜层沉积在第一铜层上 通过选择性电镀方法。 对第一和​​第二铜层进行退火,然后第二CMP步骤将第二铜层平坦化成与电介质层共面。 本发明也是由上述铜层构成的铜布线,其中第一铜层具有第二铜层的晶粒密度(G SUB D1)= G D2 D2。

    System and method for reducing irregularities on the surface of a backside illuminated photodiode
    33.
    发明授权
    System and method for reducing irregularities on the surface of a backside illuminated photodiode 有权
    用于减少背面照射光电二极管表面的凹凸的系统和方法

    公开(公告)号:US09349902B2

    公开(公告)日:2016-05-24

    申请号:US13486833

    申请日:2012-06-01

    摘要: System and method for processing a semiconductor device surface to reduce dark current and white pixel anomalies. An embodiment comprises a method applied to a semiconductor or photodiode device surface adjacent to a photosensitive region, and opposite a side having circuit structures for the device. A doped layer may optionally be created at a depth of less than about 10 nanometers below the surface of the substrate and may be doped with a boron concentration between about 1E13 and 1E16. An oxide may be created on the substrate using a temperature sufficient to reduce the surface roughness below a predetermined roughness threshold, and optionally at a temperature between about 300° C. and 500° C. and a thickness between about 1 nanometer and about 10 nanometers. A dielectric may then be created on the oxide, the dielectric having a refractive index greater than a predetermined refractive threshold, optionally at least about 2.0.

    摘要翻译: 用于处理半导体器件表面以减少暗电流和白色像素异常的系统和方法。 一个实施例包括应用于与光敏区域相邻的半导体或光电二极管器件表面的方法,以及与该器件的电路结构相反的一侧。 掺杂层可以任选地在衬底表面下方小于约10纳米的深度处产生,并且可以掺杂在约1E13和1E16之间的硼浓度。 可以使用足以将表面粗糙度降低到预定粗糙度阈值以下且可选地在约300℃至500℃之间的温度和约1纳米至约10纳米的厚度的温度在基底上产生氧化物 。 然后可以在氧化物上产生电介质,电介质具有大于预定折射阈值的折射率,任选至少约2.0。

    Image sensor and method of manufacturing
    34.
    发明授权
    Image sensor and method of manufacturing 有权
    图像传感器及制造方法

    公开(公告)号:US08847286B2

    公开(公告)日:2014-09-30

    申请号:US13349221

    申请日:2012-01-12

    IPC分类号: H01L27/148

    摘要: An image sensor includes a substrate having opposite first and second sides, a multilayer structure on the first side of the substrate, and a photo-sensitive element on the second side of the substrate. The photo-sensitive element is configured to receive light that is incident upon the first side and transmitted through the multilayer structure and the substrate. The multilayer structure includes first and second light transmitting layers. The first light transmitting layer is sandwiched between the substrate and the second light transmitting layer. The first light transmitting layer has a refractive index that is from 60% to 90% of a refractive index of the substrate. The second light transmitting layer has a refractive index that is lower than the refractive index of the first light transmitting layer and is from 40% to 70% of the refractive index of the substrate.

    摘要翻译: 图像传感器包括具有相对的第一和第二侧的基板,在基板的第一侧上的多层结构和在基板的第二侧上的感光元件。 光敏元件被配置为接收入射在第一侧并透过多层结构和基板的光。 多层结构包括第一和第二透光层。 第一透光层夹在基板和第二透光层之间。 第一透光层的折射率为基板折射率的60%至90%。 第二透光层的折射率低于第一透光层的折射率,为基板的折射率的40%〜70%。

    Methods for Minimizing Edge Peeling in the Manufacturing of BSI Chips
    35.
    发明申请
    Methods for Minimizing Edge Peeling in the Manufacturing of BSI Chips 有权
    在BSI芯片制造中最小化边缘剥离的方法

    公开(公告)号:US20140024170A1

    公开(公告)日:2014-01-23

    申请号:US13551457

    申请日:2012-07-17

    IPC分类号: H01L31/18

    摘要: A method includes forming top metal lines over a semiconductor substrate, wherein the semiconductor substrate is a portion of a wafer having a bevel. When the top metal lines are exposed, an etchant is supplied on the bevel, wherein regions of the wafer sprayed with the etchant has an inner defining line forming a first ring having a first diameter. A trimming step is performed to trim an edge portion of the wafer, wherein an edge of a remaining portion of the wafer has a second diameter substantially equal to or smaller than the first diameter.

    摘要翻译: 一种方法包括在半导体衬底上形成顶部金属线,其中半导体衬底是具有斜面的晶片的一部分。 当顶部金属线暴露时,在斜面上提供蚀刻剂,其中用蚀刻剂喷射的晶片的区域具有形成具有第一直径的第一环的内部限定线。 进行修整步骤以修剪晶片的边缘部分,其中晶片的剩余部分的边缘具有基本上等于或小于第一直径的第二直径。

    Via/contact and damascene structures
    36.
    发明授权
    Via/contact and damascene structures 有权
    通过/接触和镶嵌结构

    公开(公告)号:US08531036B2

    公开(公告)日:2013-09-10

    申请号:US13563495

    申请日:2012-07-31

    IPC分类号: H01L23/48

    CPC分类号: H01L21/76831 H01L21/7684

    摘要: A semiconductor structure is provided and includes a dielectric layer disposed over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is disposed in the opening.

    摘要翻译: 提供半导体结构,并且包括设置在基板上的电介质层。 在电介质层上形成第一非导电阻挡层。 通过第一非导电阻挡层和介电层内形成至少一个开口。 在第一非导电阻挡层上并在开口内形成第二非导电阻挡层。 去除第二非导电阻挡层的至少一部分,从而至少部分地暴露第一非导电阻挡层的顶表面和开口的底表面,而第二非导电阻挡层保留在侧壁上 的开幕。 种子层和导电层设置在开口中。

    Methods and Apparatus for an Improved Reflectivity Optical Grid for Image Sensors
    37.
    发明申请
    Methods and Apparatus for an Improved Reflectivity Optical Grid for Image Sensors 有权
    用于图像传感器的改进的反射光学网格的方法和装置

    公开(公告)号:US20130193538A1

    公开(公告)日:2013-08-01

    申请号:US13363280

    申请日:2012-01-31

    IPC分类号: H01L31/0232 H01L31/18

    摘要: An improved reflectivity optical grid for image sensors. In an embodiment, a backside illuminated CIS device includes a semiconductor substrate having a pixel array area comprising a plurality of photosensors formed on a front side surface of the semiconductor substrate, each of the photosensors forming a pixel in the pixel array area; an optical grid material disposed over a backside surface of the semiconductor substrate, the optical grid material patterned to form an optical grid that bounds each of the pixels in the pixel array area and extending above the semiconductor substrate, the optical grid having sidewalls and a top portion; and a highly reflective coating formed over the optical grid, comprising a pure metal coating of a metal that is at least 99% pure, and a high-k dielectric coating over the pure metal coating that has a refractive index of greater than about 2.0. Methods are also disclosed.

    摘要翻译: 用于图像传感器的改进的反射光栅。 在一个实施例中,背面照明的CIS器件包括具有像素阵列区域的半导体衬底,该像素阵列区域包括形成在半导体衬底的前侧表面上的多个光电传感器,每个光电传感器在像素阵列区域中形成像素; 设置在半导体衬底的背侧表面上的光栅格材料,所述光栅格材料被图案化以形成限定像素阵列区域中的每个像素并在半导体衬底上方延伸的光栅,所述光栅具有侧壁和顶部 一部分; 以及形成在光栅上的高反射涂层,包括纯金属的纯金属涂层,其纯度至少为99%,纯金属涂层上的高k电介质涂层具有大于约2.0的折射率。 还公开了方法。

    SEMICONDUCTOR MANUFACTURING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    38.
    发明申请
    SEMICONDUCTOR MANUFACTURING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
    半导体制造装置及制造半导体器件的方法

    公开(公告)号:US20130102152A1

    公开(公告)日:2013-04-25

    申请号:US13277609

    申请日:2011-10-20

    CPC分类号: B24B37/32

    摘要: A semiconductor manufacturing apparatus includes at least one inner retaining ring, and an outer retaining ring. The at least one inner retaining ring applies a first pressure to the polishing pad, and retains a substrate on the polishing pad. The outer retaining ring applies a second pressure to the polishing pad, and retains the at least one inner retaining ring on the polishing pad. Control of the first pressure is independent with respect to control of the second pressure.

    摘要翻译: 半导体制造装置包括至少一个内保持环和外保持环。 至少一个内部保持环向抛光垫施加第一压力,并将衬底保持在抛光垫上。 外保持环向抛光垫施加第二压力,并且将至少一个内保持环保持在抛光垫上。 关于第二压力的控制,第一压力的控制是独立的。

    Apparatus for Wafer Grinding
    39.
    发明申请

    公开(公告)号:US20130023188A1

    公开(公告)日:2013-01-24

    申请号:US13188028

    申请日:2011-07-21

    IPC分类号: B24B1/00 B24B7/00

    CPC分类号: B24B7/228 B24D7/14

    摘要: A grinding wheel comprises an outer base with a first attached grain pad; and an inner frame with a second attached grain pad; and a spindle axis shared by the outer base and the inner frame, wherein at least one of the outer base and the inner frame can move independently along the shared spindle axis; and wherein the outer base, the inner frame, and the shared spindle axis all have a same center. A grinding system comprises an above said grinding wheel, and a wheel head attached to the shared spindle axis, capable of moving vertically, in addition to a motor driving the grinding wheel to spin; and a chuck table for fixing a wafer on top of the chuck table; wherein the grinding wheel overlaps a portion of the chuck table, each capable of spinning to the opposite direction of another.

    VIA/CONTACT AND DAMASCENE STRUCTURES
    40.
    发明申请
    VIA/CONTACT AND DAMASCENE STRUCTURES 有权
    威盛/联系人和大马士革结构

    公开(公告)号:US20120292768A1

    公开(公告)日:2012-11-22

    申请号:US13563495

    申请日:2012-07-31

    IPC分类号: H01L23/52

    CPC分类号: H01L21/76831 H01L21/7684

    摘要: A semiconductor structure is provided and includes a dielectric layer disposed over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is disposed in the opening.

    摘要翻译: 提供半导体结构,并且包括设置在基板上的电介质层。 在电介质层上形成第一非导电阻挡层。 通过第一非导电阻挡层和介电层内形成至少一个开口。 在第一非导电阻挡层上并在开口内形成第二非导电阻挡层。 去除第二非导电阻挡层的至少一部分,从而至少部分地暴露第一非导电阻挡层的顶表面和开口的底表面,而第二非导电阻挡层保留在侧壁上 的开幕。 种子层和导电层设置在开口中。