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223 条记录 (耗时 0.028 秒)

    Flash memory devices, methods of erasing flash memory devices and memory systems including the same
    31.
    发明授权
    Flash memory devices, methods of erasing flash memory devices and memory systems including the same 有权
    闪存设备，擦除闪存设备的方法和包括其的存储器系统

    公开(公告)号：US07529138B2

    公开(公告)日：2009-05-05

    申请号：US11704343

    申请日：2007-02-09

    申请人： Ki-Tae Park ,  Jung-Dal Choi

    发明人： Ki-Tae Park ,  Jung-Dal Choi

    IPC分类号： G11C11/34

    CPC分类号： G11C16/16 ,  G11C16/0483

    摘要： In a method of erasing a non-volatile memory device an electric field is applied between a plurality of word lines and a substrate to erase memory cells in a memory block simultaneously. After a first time period elapses, the electric field applied between a first portion of the plurality of word lines and the substrate is maintained to erase memory cells, while the electric field between a second portion of the plurality of word lines and the substrate is removed or reduced.

    摘要翻译： 在擦除非易失性存储器件的方法中，在多个字线和衬底之间施加电场以同时擦除存储器块中的存储器单元。 在经过第一时间段之后，保持施加在多个字线的第一部分和基板之间的电场以擦除存储单元，同时多个字线的第二部分与基板之间的电场被去除 或减少。

    NONVOLATILE MEMORY DEVICE WITH MULTIPLE PAGE REGIONS, AND METHODS OF READING AND PRECHARGING THE SAME
    33.
    发明申请
    NONVOLATILE MEMORY DEVICE WITH MULTIPLE PAGE REGIONS, AND METHODS OF READING AND PRECHARGING THE SAME 有权
    具有多个页面区域的非易失性存储器件及其读取和预处理方法

    公开(公告)号：US20090091981A1

    公开(公告)日：2009-04-09

    申请号：US12236771

    申请日：2008-09-24

    申请人： Ki-Tae Park ,  Hyun-Kyoung Kim

    发明人： Ki-Tae Park ,  Hyun-Kyoung Kim

    IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C7/00

    CPC分类号： G11C16/3418

    摘要： A nonvolatile memory device includes a memory cell array having multiple memory cells arranged at intersections of word lines and bit lines, a first page region configured with at least two adjacent memory cells coupled to a word line, and a second page region configured with at least two adjacent memory cells coupled to the word line. The nonvolatile memory devices also includes a first common source line connecting with the memory cells of the first page region, and a second common source line connecting with the memory cells of the second page region. The first and second common source lines are controlled independently.

    摘要翻译： 非易失性存储器件包括存储单元阵列，其具有布置在字线和位线的交点处的多个存储器单元，配置有耦合到字线的至少两个相邻存储器单元的第一页区域和至少配置有第二页区域 耦合到字线的两个相邻的存储单元。 非易失性存储器件还包括与第一页区域的存储单元连接的第一公共源极线和与第二页区域的存储器单元连接的第二公共源极线。 第一和第二公共源极线独立控制。

    NAND flash memory device having dummy memory cells and methods of operating same
    34.
    发明授权
    NAND flash memory device having dummy memory cells and methods of operating same 有权
    具有虚拟存储单元的NAND闪存器件及其操作方法

    公开(公告)号：US07480178B2

    公开(公告)日：2009-01-20

    申请号：US11279607

    申请日：2006-04-13

    申请人： Ki-Tae Park ,  Jung-Dal Choi ,  Jong-Sun Sel ,  Yoo-Cheol Shin

    发明人： Ki-Tae Park ,  Jung-Dal Choi ,  Jong-Sun Sel ,  Yoo-Cheol Shin

    IPC分类号： G11C16/06

    CPC分类号： G11C16/0483 ,  G11C16/107 ,  G11C16/12 ,  G11C16/3445

    摘要： A NAND flash memory device includes a control circuit configured to apply, during a program operation, a first word line voltage to non-selected ones of a plurality of serially-connected memory cells, a second word line voltage greater than the first word line voltage to a selected one of the plurality of memory cells, and a third word line voltage lower than the first word line voltage to a dummy memory cell connected in series with the plurality of memory cells. In other embodiments, a control circuit is configured to program a dummy memory cell before and/or after each erase operation on a plurality of memory cells connected in series therewith. In still other embodiments, a control circuit is configured to forego erasure of a dummy memory cell while erasing a plurality of memory cells connected in series therewith.

    摘要翻译： NAND闪速存储器件包括控制电路，其被配置为在编程操作期间将第一字线电压施加到多个串联存储器单元中的未选择的电压，第二字线电压大于第一字线电压 到多个存储单元中的一个选择的一个，以及比第一字线电压低的第三字线电压到与多个存储单元串联连接的虚拟存储单元。 在其他实施例中，控制电路被配置为在与每个擦除操作之间的每个擦除操作之前和/或之后对与其串联的多个存储器单元进行编程。 在其他实施例中，控制电路被配置为在擦除与其串联连接的多个存储器单元时，放弃擦除伪存储器单元。

    NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING
    35.
    发明申请
    NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING 有权
    非易失性存储器件和操作方法

    公开(公告)号：US20080316818A1

    公开(公告)日：2008-12-25

    申请号：US12141737

    申请日：2008-06-18

    申请人： Ki-Tae PARK ,  Doo-Gon KIM ,  Yeong-Taek LEE

    发明人： Ki-Tae PARK ,  Doo-Gon KIM ,  Yeong-Taek LEE

    IPC分类号： G11C16/06

    CPC分类号： G11C16/3418

    摘要： A non volatile memory device and method of operating including providing a verification voltage to a gate of a selected memory cell within multiple memory cells and providing a first pass voltage to a gate of a non-selected memory cell within the memory cells during a program verification operation; and providing a read voltage to the gate of the selected memory cell and providing a second pass voltage to the gate of the non-selected memory cell during a read operation. The second pass voltage is greater than the first pass voltage.

    摘要翻译： 一种非易失性存储器件和操作方法，包括向多个存储器单元内的所选存储单元的栅极提供验证电压，并且在程序验证期间向存储器单元内的未选择存储单元的栅极提供第一通过电压 操作; 以及向所选择的存储单元的栅极提供读取电压，并且在读取操作期间向未选择的存储单元的栅极提供第二通过电压。 第二通过电压大于第一通过电压。

    3-LEVEL NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING THE SAME
    37.
    发明申请
    3-LEVEL NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING THE SAME 失效
    3级非挥发性半导体存储器件及其驱动方法

    公开(公告)号：US20070025161A1

    公开(公告)日：2007-02-01

    申请号：US11460580

    申请日：2006-07-27

    申请人： Ki-Tae PARK ,  Jung-Dal CHOi ,  Sung-Kyu JO

    发明人： Ki-Tae PARK ,  Jung-Dal CHOi ,  Sung-Kyu JO

    IPC分类号： G11C7/10

    CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/24

    摘要： A page buffer for a non-volatile semiconductor memory device includes a switch configured to couple a first bitline coupled to a first memory cell to a second bitline coupled to a second memory cell, a first latch block coupled to the first bitline and configured to transfer a first latch data to the first memory cell, and a second latch block coupled to the second bitline and the first latch block, and configured to transfer a second latch data to the second memory cell.

    摘要翻译： 用于非易失性半导体存储器件的页面缓冲器包括被配置为将耦合到第一存储器单元的第一位线耦合到耦合到第二存储器单元的第二位线的开关，耦合到第一位线并被配置为传送的第一锁存块 向第一存储器单元提供第一锁存数据，以及耦合到第二位线和第一锁存块的第二锁存块，并且被配置为将第二锁存数据传送到第二存储器单元。

    Complementary pass transistor based flip-flop
    39.
    发明授权
    Complementary pass transistor based flip-flop 有权

    公开(公告)号：US06646492B2

    公开(公告)日：2003-11-11

    申请号：US10396628

    申请日：2003-03-25

    申请人： Ki-tae Park ,  Hyo-sik Won

    发明人： Ki-tae Park ,  Hyo-sik Won

    IPC分类号： H02J338

    CPC分类号： H03K3/356156 ,  H03K3/012

    摘要： A complementary pass transistor based flip-flop (CP flip-flop) having a relatively small layout area and operable at a high speed with reduced power consumption is provided. The CP flip-flop does not need an additional circuit for retaining latched data in a sleep mode. The CP flip-flop receives a clock signal, delays the clock signal for a predetermined time period, and detects the delay time period from the clock signal. The CP flip-flop receives input data for the predetermined delay time and latches the input data until new input data is received. The CP flip-flop is advantageous in that the design of timing for retaining data can be simplified.