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    ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICE
    31.
    发明申请
    ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICE 有权
    静电放电（ESD）保护装置

    公开(公告)号：US20130088800A1

    公开(公告)日：2013-04-11

    申请号：US13270298

    申请日：2011-10-11

    Applicant: Chang-Tzu WANG ,  Tien-Hao Tang ,  Kuan-Cheng Su

    Inventor： Chang-Tzu WANG ,  Tien-Hao Tang ,  Kuan-Cheng Su

    IPC: H02H9/00

    CPC classification number: H02H9/00 ,  H01L27/0266

    Abstract: An exemplary ESD protection device is adapted for a high-voltage tolerant I/O circuit and includes a stacked transistor and a gate-grounded transistor e.g., a non-lightly doped drain type gate-grounded transistor. The stacked transistor and the gate-grounded transistor are electrically coupled in parallel between an I/O pad and a grounding voltage of the high-voltage tolerant I/O circuit.

    Abstract translation: 示例性ESD保护装置适用于高耐压I / O电路，并且包括堆叠晶体管和栅极接地晶体管，例如非轻掺杂漏极型栅极接地晶体管。 堆叠晶体管和栅极接地晶体管在I / O焊盘和高耐压I / O电路的接地电压之间并联电耦合。

    Test structure
    33.
    发明授权
    Test structure 失效
    测试结构

    公开(公告)号：US07649377B2

    公开(公告)日：2010-01-19

    申请号：US12266514

    申请日：2008-11-06

    Applicant: Wen-Hsiung Ko ,  Wen-Chun Chang ,  Kuan-Cheng Su

    Inventor： Wen-Hsiung Ko ,  Wen-Chun Chang ,  Kuan-Cheng Su

    IPC: G01R31/26

    CPC classification number: G01R31/2875 ,  H01L22/14 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A wafer level test structure in which, a heating plate is formed on the wafer for heating a structure to be tested positioned above or adjacent to the heating plate. The heating plate produces heat by electrically connecting to a current. Thus, the heat provided by the heating plate and the electric input/output into/from the structure to be tested are controlled separately and not influenced each other.

    Abstract translation: 一种晶片级测试结构，其中在晶片上形成加热板，用于加热被测定的结构被定位在加热板上方或附近。 加热板通过电连接到电流产生热量。 因此，加热板提供的热量和进入/待测结构的电输入/输出分开控制，彼此不相互影响。

    WAFER-LEVEL RELIABILITY YIELD ENHANCEMENT SYSTEM AND RELATED METHOD
    35.
    发明申请
    WAFER-LEVEL RELIABILITY YIELD ENHANCEMENT SYSTEM AND RELATED METHOD 审中-公开
    水平可靠性增强系统及相关方法

    公开(公告)号：US20080270056A1

    公开(公告)日：2008-10-30

    申请号：US11740916

    申请日：2007-04-26

    Applicant: Yun-Chi Yang ,  Cheng-Li Lin ,  Chia-Jen Kao ,  Ju-Ping Chen ,  Kuan-Cheng Su

    Inventor： Yun-Chi Yang ,  Cheng-Li Lin ,  Chia-Jen Kao ,  Ju-Ping Chen ,  Kuan-Cheng Su

    IPC: H01L21/66 ,  G01N37/00

    CPC classification number: H01L22/20

    Abstract: A yield enhancement system has a fabrication line with semiconductor fabrication devices for fabricating a wafer, an inspection and measurement monitoring system coupled to the fabrication line for determining process data corresponding to semiconductor fabrication devices, and a post-process testing line coupled to the fabrication line for performing in-line wafer-level testing. The post-process testing line includes a wafer acceptance tester, a yield monitor coupled to the wafer acceptance tester, and a wafer level reliability tester coupled to the wafer acceptance tester for estimating a life span of a device on the wafer.

    Abstract translation: 屈服增强系统具有制造线，其具有用于制造晶片的半导体制造装置，耦合到制造线的检查和测量监测系统，用于确定对应于半导体制造装置的工艺数据，以及耦合到制造线的后处理测试线 用于进行在线晶圆级测试。 后处理测试线包括晶片接收测试仪，耦合到晶片接收测试仪的屈服监测器，以及耦合到晶片接收测试仪的晶片级可靠性测试器，用于估计晶片上的器件的寿命。

    Method of reducing junction capacitance of source/drain region
    36.
    发明授权
    Method of reducing junction capacitance of source/drain region 有权
    减少源极/漏极区的结电容的方法

    公开(公告)号：US06383883B1

    公开(公告)日：2002-05-07

    申请号：US09173831

    申请日：1998-10-16

    Applicant: Yao-Chin Cheng ,  Kuan-Cheng Su

    Inventor： Yao-Chin Cheng ,  Kuan-Cheng Su

    IPC: H01L2100

    CPC classification number: H01L29/6659 ,  H01L29/7833

    Abstract: A method of reducing junction capacitance of a source/drain region. A gate oxide layer is formed on a first conductive type substrate. A polysilicon layer is formed and patterned on the gate. Light second conductive type ions are implanted into the substrate with the polysilicon layer as a mask. An insulation layer is formed to cover a side wall of the polysilicon layer. A first step heavy of ion implantation with second conductive type ions is perform to the substrate using the polysilicon layer and the spacer as mask, so that a heavily doped region is formed. A second step of heavy ion implantation with the second conductive type ions is performed to the substrate using the polysilicon layer and the spacer as masks, so that the heavily doped region is broadened and deepened with a smooth ion distribution profile.

    Abstract translation: 一种减少源/漏区的结电容的方法。 栅极氧化层形成在第一导电类型的衬底上。 在栅极上形成并图案化多晶硅层。 将光第二导电型离子注入到具有多晶硅层作为掩模的衬底中。 形成绝缘层以覆盖多晶硅层的侧壁。 利用第二导电型离子进行离子注入的第一步是使用多晶硅层和间隔物作为掩模进行衬底，从而形成重掺杂区域。 使用多晶硅层和间隔物作为掩模，对基板进行与第二导电型离子的重离子注入的第二步骤，使得重掺杂区域以平滑的离子分布分布变宽和加深。

    Buried contact method to release plasma-included charging damage on device
    37.
    发明授权
    Buried contact method to release plasma-included charging damage on device 失效
    埋置接触方式释放等离子体对设备的充电损坏

    公开(公告)号：US6093626A

    公开(公告)日：2000-07-25

    申请号：US897229

    申请日：1997-07-29

    Applicant: Kuan-Cheng Su ,  Shing-Ren Sheu

    Inventor： Kuan-Cheng Su ,  Shing-Ren Sheu

    IPC: H01L27/02 ,  H01L21/331 ,  H01L21/22 ,  H01L21/26

    CPC classification number: H01L27/0255

    Abstract: A method for eliminating plasma-induced charging damage during manufacture of an integrated circuit is described. A semiconductor substrate having a first conductivity type is provided. An oxide layer is formed on the semiconductor substrate. An opening is formed in the oxide layer. A polysilicon layer is formed over the oxide layer and in the opening. A diffusion region is formed in the semiconductor substrate, connected to the polysilicon layer through the opening, having a second conductivity type opposite to the first conductivity type, whereby a buried contact is formed. The buried contact is connected, through the substrate, to a ground reference. Further processing in a plasma environment is performed that would normally produce charging damage to the integrated circuit, but whereby the buried contact prevents the charging damage.

    Abstract translation: 描述了在集成电路的制造期间消除等离子体引起的充电损坏的方法。 提供具有第一导电类型的半导体衬底。 在半导体基板上形成氧化物层。 在氧化物层中形成开口。 在氧化物层和开口中形成多晶硅层。 扩散区形成在半导体衬底中，通过开口与多晶硅层连接，具有与第一导电类型相反的第二导电类型，由此形成掩埋接触。 埋入触点通过基板连接到地面参考。 进行等离子体环境中的进一步处理，这通常会对集成电路造成充电损坏，但由此埋入触点防止充电损坏。

    Field effect transistor with recessed buried source and drain regions
    38.
    发明授权
    Field effect transistor with recessed buried source and drain regions 失效
    具有埋入式源极和漏极区域的场效应晶体管

    公开(公告)号：US5705840A

    公开(公告)日：1998-01-06

    申请号：US636785

    申请日：1996-04-23

    Applicant: Shing-Ren Shen ,  Kuan-Cheng Su ,  Chen-Hui Chung

    Inventor： Shing-Ren Shen ,  Kuan-Cheng Su ,  Chen-Hui Chung

    IPC: H01L21/336 ,  H01L29/08 ,  H01L29/10 ,  H01L29/76 ,  H01L29/94

    CPC classification number: H01L29/66636 ,  H01L29/0847 ,  H01L29/1083

    Abstract: The invention describes recessed source/drain regions formed in trenches in the substrate that provide a smooth surface topology, smaller devils and improved device performance. The recessed source/drain regions have two conductive regions: the first upper lightly doped region on the trench sidewalls, and the second lower region under the trench bottom. In addition, two buried layers are formed between adjacent source/drain regions: a threshold voltage layer near the substrate surface and an anti-punchthrough layer formed at approximately the same depth as the lower source/drain regions on the trench bottoms. The upper lightly doped source/drain region and the anti-punchthrough layer have the effect of increasing the punchthrough voltage without increasing the threshold voltage. The upper and lower source/drain regions lower the overall resistivity of the source/drain allowing use of smaller line pitches and therefore smaller devils. Overall, the recessed source/drain regions and the two buried layers allow the formation of smaller devices with improved performance.

    Abstract translation: 本发明描述了形成在衬底中的沟槽中的凹陷源极/漏极区域，其提供光滑的表面拓扑，较小的恶魔和改进的器件性能。 凹陷的源极/漏极区域具有两个导电区域：沟槽侧壁上的第一上部轻掺杂区域和沟槽底部下方的第二下部区域。 此外，在相邻的源极/漏极区之间形成两个掩埋层：在衬底表面附近的阈值电压层和形成在与沟槽底部上的下部源极/漏极区域大致相同深度的抗穿通层。 上部轻掺杂源极/漏极区域和抗穿通层具有增加穿透电压而不增加阈值电压的效果。 上下源极​​/漏极区域降低了源极/漏极的整体电阻率，从而允许使用更小的线间距并因此使用较小的磁体。 总的来说，凹陷的源极/漏极区域和两个掩埋层允许形成具有改进的性能的较小器件。

    Multi-state read-only memory using multiple polysilicon selective depositions
    39.
    发明授权
    Multi-state read-only memory using multiple polysilicon selective depositions 失效
    多状态只读存储器，使用多个多晶硅选择性沉积

    公开(公告)号：US5545580A

    公开(公告)日：1996-08-13

    申请号：US530746

    申请日：1995-09-19

    Applicant: Yi-Chung Sheng ,  Chen-Hui Chung ,  Kuan-Cheng Su

    Inventor： Yi-Chung Sheng ,  Chen-Hui Chung ,  Kuan-Cheng Su

    IPC: H01L27/112 ,  H01L21/8246

    CPC classification number: H01L27/112

    Abstract: A multi-state read-only-memory device and a method for fabricating the same is suitable for forming on a semiconductor substrate. The read-only memory device is provided with bit lines and word lines which are mutually intersecting. In accordance with the present invention, multiple polysilicon selective deposition procedures are utilized to form a plurality of protrusion portions onto the word lines but with multiple thicknesses. Then, one implantation procedure is applied to program the device into multiple states at the same time without incurring misalignment problems that result in inaccuracy.

    Abstract translation: 多状态只读存储器件及其制造方法适用于在半导体衬底上形成。 只读存储器件具有相互相交的位线和字线。 根据本发明，利用多个多晶硅选择性沉积程序在字线上形成多个突出部分，但具有多个厚度。 然后，应用一个植入程序同时将器件编程成多个状态，而不会导致导致不准确的错位问题。

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