公开(公告)号：US20070002611A1

公开(公告)日：2007-01-04

申请号：US11172742

申请日：2005-06-30

Applicant: Yibin Ye ,  Muhammad Khellah ,  Dinesh Somasekhar ,  Ali Keshavarzi ,  Fabrice Paillet ,  Vivek De

Inventor： Yibin Ye ,  Muhammad Khellah ,  Dinesh Somasekhar ,  Ali Keshavarzi ,  Fabrice Paillet ,  Vivek De

IPC: G11C11/34

CPC classification number: G11C11/405 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094

Abstract: A cell in an information storage cell array is written, by asserting a signal on a bit line that is coupled to the cell and to a group of other cells in the array, to a first voltage. The cell is read by asserting a signal on a word line that is coupled to the cell and to another group of cells in the array, in a direction of, but without reaching, the first voltage. Other embodiments are also described and claimed.

公开(公告)号：US20060054933A1

公开(公告)日：2006-03-16

申请号：US11268098

申请日：2005-11-07

Applicant: Ali Keshavarzi ,  Stephen Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Vivek De

Inventor： Ali Keshavarzi ,  Stephen Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Vivek De

IPC: H01L27/10

CPC classification number: G11C11/404 ,  G11C2211/4016 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L29/7841

Abstract: Some embodiments provide a memory cell that includes a body region, a source region and a drain region. The body region is doped with charge carriers of a first type, the source region is disposed in the body region and doped with charge carriers of a second type, and the drain region is disposed in the body region and doped with charge carriers of the second type. The body region and the source region form a first junction, the body region and the drain region form a second junction, and a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased.

公开(公告)号：US20060002211A1

公开(公告)日：2006-01-05

申请号：US10881001

申请日：2004-06-30

Applicant: Yibin Ye ,  Dinesh Somasekhar ,  Muhammad Khellah ,  Fabrice Paillet ,  Stephen Tang ,  Ali Keshavarzi ,  Shih-Lien Lu ,  Vivek De

Inventor： Yibin Ye ,  Dinesh Somasekhar ,  Muhammad Khellah ,  Fabrice Paillet ,  Stephen Tang ,  Ali Keshavarzi ,  Shih-Lien Lu ,  Vivek De

IPC: G11C7/00

CPC classification number: G11C11/405

Abstract: A two transistor memory cell includes a write transistor and a read transistor. When reading the memory cell, the read transistor is turned on, and a voltage develops on a read bit line.

公开(公告)号：US20050213370A1

公开(公告)日：2005-09-29

申请号：US10810093

申请日：2004-03-26

Applicant: Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Ali Farhang ,  Gunjan Pandya ,  Vivek De

Inventor： Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Ali Farhang ,  Gunjan Pandya ,  Vivek De

IPC: G11C11/41 ,  G11C11/419

CPC classification number: G11C11/419

Abstract: A SRAM memory cell comprising cross-coupled inverters, each cross-coupled inverter comprising a pull-up transistor, where the pull-up transistors are forward body biased during read operations. Forward body biasing improves the read stability of the memory cell. Other embodiments are described and claimed.

Abstract translation: 一种SRAM存储单元，包括交叉耦合的反相器，每个交叉耦合的反相器包括一个上拉晶体管，其中上拉晶体管在读取操作期间被正向偏置。 正向主体偏置改善了存储单元的读取稳定性。 描述和要求保护其他实施例。

公开(公告)号：US20050146956A1

公开(公告)日：2005-07-07

申请号：US10746148

申请日：2003-12-24

Applicant: Dinesh Somasekhar ,  Yibin Ye ,  Muhammad Khellah ,  Fabrice Paillet ,  Stephen Tang ,  Ali Keshavarzi ,  Shih-Lien Lu ,  Vivek De

Inventor： Dinesh Somasekhar ,  Yibin Ye ,  Muhammad Khellah ,  Fabrice Paillet ,  Stephen Tang ,  Ali Keshavarzi ,  Shih-Lien Lu ,  Vivek De

IPC: G11C7/00 ,  G11C7/12

CPC classification number: G11C7/12

Abstract: Some embodiments provide pre-charge of a bit-line coupled to a memory cell to a reference voltage using a pre-charge device, discharge of the bit-line based on a value stored by the memory cell, injection during the discharge, of a first current into the bit-line using the pre-charge device, and injection, during the discharge, of a second current into a reference bit-line using a second pre-charge device. Also during the discharge, a difference is sensed between a voltage on the bit-line and a voltage on the reference bit-line.

Abstract translation: 一些实施例使用预充电器件将耦合到存储器单元的位线预充电至参考电压，基于存储器单元存储的值，放电期间的注入，放电期间的位线放电， 使用预充电器件进入位线的第一电流，以及在放电期间使用第二预充电器件将第二电流注入参考位线。 此外，在放电期间，在位线上的电压和参考位线上的电压之间感测到差异。

公开(公告)号：US20050111255A1

公开(公告)日：2005-05-26

申请号：US10721184

申请日：2003-11-26

Applicant: Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Vivek De

Inventor： Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Vivek De

IPC: G11C11/404 ,  H01L27/108 ,  G11C11/34

CPC classification number: H01L27/108 ,  G11C11/404

Abstract: Embodiments relate to a Floating Body Dynamic Random Access Memory (FBDRAM). The FBDRAM utilizes a purge line to reset a FBDRAM cell, prior to writing data to the FBDRAM cell.

Abstract translation: 实施例涉及浮体动态随机存取存储器（FBDRAM）。 在将数据写入FBDRAM单元之前，FBDRAM利用清除线来复位FBDRAM单元。

公开(公告)号：US08667367B2

公开(公告)日：2014-03-04

申请号：US13215949

申请日：2011-08-23

Applicant: Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Nam Sung Kim ,  Vivek De

Inventor： Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Nam Sung Kim ,  Vivek De

IPC: G11C29/00

CPC classification number: G11C29/42 ,  G11C11/4125 ,  G11C11/417 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/12005 ,  G11C29/50 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2029/5004

Abstract: Described herein is an apparatus for adjusting a power supply level for a memory cell to improve stability of a memory unit. The apparatus comprises memory circuitry including memory cells, error detection circuitry to detect error in data stored by memory cells of the memory circuitry, and supply voltage control circuitry to increase supply voltage for one or more memory cells of the memory circuitry based at least in part on detected error.

Abstract translation: 这里描述了一种用于调整存储器单元的电源电平以提高存储器单元的稳定性的装置。 该装置包括存储器电路，其包括存储器单元，用于检测由存储器电路的存储器单元存储的数据中的错误的误差检测电路，以及供应电压控制电路，用于至少部分地增加存储器电路的一个或多个存储器单元的电源电压 检测到错误。

公开(公告)号：US20080162986A1

公开(公告)日：2008-07-03

申请号：US11648490

申请日：2006-12-28

Applicant: Nam Sung Kim ,  Muhammad Khellah ,  Yibin Ye ,  Dinesh Somasekhar ,  Vivek De

Inventor： Nam Sung Kim ,  Muhammad Khellah ,  Yibin Ye ,  Dinesh Somasekhar ,  Vivek De

IPC: G06F11/00

CPC classification number: G11C11/419 ,  G11C11/41 ,  G11C29/38 ,  G11C29/50 ,  G11C2029/0409

Abstract: For one disclosed embodiment, an apparatus may comprise a memory cell to store a bit value, wherein the memory cell may lose the bit value in response to a memory access operation. The apparatus may also comprise first circuitry to detect whether the memory cell loses the bit value in response to the memory access operation and second circuitry to restore the bit value in the memory cell in response to detection that the memory cell loses the bit value. Other embodiments are also disclosed.

Abstract translation: 对于一个所公开的实施例，装置可以包括存储单元以存储位值，其中存储单元可以响应于存储器访问操作而丢失位值。 该装置还可以包括第一电路，用于响应于存储器单元丢失比特值的检测，检测存储器单元是否响应于存储器访问操作而丢失比特值以及第二电路来恢复存储器单元中的比特值。 还公开了其他实施例。

公开(公告)号：US20070004162A1

公开(公告)日：2007-01-04

申请号：US11170504

申请日：2005-06-29

Applicant: Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Vivek De

Inventor： Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Vivek De

IPC: H01L21/331

CPC classification number: H01L27/108 ,  H01L27/1085 ,  H01L28/40

Abstract: A manufacturing process modification is disclosed for producing a metal-insulator-metal (MIM) capacitor. The MIM capacitor may be used in memory cells, such as DRAMs, and may also be integrated into logic processing, such as for microprocessors. The processing used to generate the MIM capacitor is adaptable to current logic processing techniques. Other embodiments are described and claimed.

Abstract translation: 公开了制造金属绝缘体金属（MIM）电容器的制造工艺改进。 MIM电容器可以用在诸如DRAM的存储器单元中，并且还可以被集成到诸如微处理器的逻辑处理中。 用于生成MIM电容器的处理适用于当前的逻辑处理技术。 描述和要求保护其他实施例。

公开(公告)号：US20060262610A1

公开(公告)日：2006-11-23

申请号：US11134450

申请日：2005-05-23

Applicant: Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Vivek De ,  James Tschanz ,  Stephen Tang

Inventor： Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Vivek De ,  James Tschanz ,  Stephen Tang

IPC: G11C5/14

CPC classification number: G11C5/14 ,  G11C8/12

Abstract: A method and apparatus for reducing power consumption in integrated memory devices is provided. Banks of memory cells may be individually put into “sleep” mode via respective “sleep” transistors.

Abstract translation: 提供了一种降低集成存储器件功耗的方法和装置。 存储单元组可以通过相应的“睡眠”晶体管单独地进入“睡眠”模式。