公开(公告)号：US20060156090A1

公开(公告)日：2006-07-13

申请号：US11002692

申请日：2004-12-02

Applicant: Louis Bushard ,  Sang Dhong ,  Brian Flachs ,  Osamu Takahashi ,  Michael White

Inventor： Louis Bushard ,  Sang Dhong ,  Brian Flachs ,  Osamu Takahashi ,  Michael White

IPC: G11C29/00

CPC classification number: G11C29/08 ,  G11C7/20 ,  G11C2029/0407

Abstract: The present invention provides for a method for memory array verification. Initialization commands are received and memory array initialization settings are generated based on received initialization commands. The memory array initialization settings are stored in a memory array. A deterministic read output function for the memory array is identified and a logic built-in self test scan on the memory array is performed based on the identified deterministic read output function.

Abstract translation: 本发明提供了一种用于存储器阵列校验的方法。 接收初始化命令，并根据接收到的初始化命令生成内存阵列初始化设置。 存储器阵列初始化设置存储在存储器阵列中。 识别存储器阵列的确定性读输出功能，并且基于所识别的确定性读输出功能来执行存储器阵列上的逻辑内置自检扫描。

公开(公告)号：US20060152247A1

公开(公告)日：2006-07-13

申请号：US11033612

申请日：2005-01-12

Applicant: Hiroaki Murakami ,  Osamu Takahashi ,  Shoji Onishi

Inventor： Hiroaki Murakami ,  Osamu Takahashi ,  Shoji Onishi

IPC: H03K19/173

CPC classification number: H03K19/1737

Abstract: Systems and methods for reducing the power consumption associated with the capacitance of sections of a multiplexer are disclosed. At each cycle, a timing signal is selectively sent only to sections of the multiplexer that include active logic. A plurality of control signals is received for processing by a corresponding plurality of input selection circuits. A plurality of additional inputs corresponding to the plurality of input selection circuits may also be received. In one embodiment, each input selection circuit is configured to output a corresponding input signal if a corresponding control signal is asserted and a timing signal is made available to the input selection circuit. To avoid unnecessary power consumption associated with the capacitance of various portions of the multiplexer, the timing signal is only asserted to a portion of the multiplexer at any given clock cycle according to the values of the control signals.

Abstract translation: 公开了用于降低与多路复用器的部分的电容相关联的功耗的系统和方法。 在每个周期，定时信号仅选择性地仅发送到包括有效逻辑的多路复用器的部分。 多个控制信号被接收用于由相应的多个输入选择电路进行处理。 还可以接收对应于多个输入选择电路的多个附加输入。 在一个实施例中，每个输入选择电路被配置为如果相应的控制信号被断言并且使定时信号对输入选择电路可用，则输出相应的输入信号。 为了避免与多路复用器的各个部分的电容相关联的不必要的功率消耗，定时信号仅根据控制信号的值以任何给定的时钟周期被认定到多路复用器的一部分。

公开(公告)号：US07053668B2

公开(公告)日：2006-05-30

申请号：US10852863

申请日：2004-05-25

Applicant: Takaaki Nakazato ,  Toru Asano ,  Osamu Takahashi ,  Sang Dhong

Inventor： Takaaki Nakazato ,  Toru Asano ,  Osamu Takahashi ,  Sang Dhong

IPC: G01R19/00 ,  G11C7/00 ,  H03F3/45

CPC classification number: H03K3/012 ,  G11C7/065 ,  H03K3/356139

Abstract: Systems and methods for increasing the amount of current that can flow through the data line pull-down transistors in a sense amplifier by tying the bodies of these transistors to a voltage other than ground. In one embodiment, the bodies of the data line pull-down transistors in a sense amplifier are tied to the intermediate nodes on the opposing side of the sense amplifier to increase the current flow through the data line pull-down transistors, and also to reduce the voltage at the intermediate node that will be pulled low by the action of the bit line transistors. In one embodiment, the sense amplifier also includes pre-charge circuits which pre-charge the intermediate nodes to a predetermined voltage that is not reduced by the threshold voltage of the pull-down transistors.

Abstract translation: 用于通过将这些晶体管的主体连接到除地之外的电压来增加可以流过读出放大器中的数据线下拉晶体管的电流量的系统和方法。 在一个实施例中，读出放大器中的数据线下拉晶体管的主体被连接到读出放大器的相对侧上的中间节点，以增加通过数据线下拉晶体管的电流，并且还减少 通过位线晶体管的动作将中间节点处的电压拉低。 在一个实施例中，读出放大器还包括将中间节点预充电到未被下拉晶体管的阈值电压降低的预定电压的预充电电路。

公开(公告)号：US07030658B2

公开(公告)日：2006-04-18

申请号：US10764179

申请日：2004-01-23

Applicant: Hiroaki Murakami ,  Osamu Takahashi ,  Jieming Qi

Inventor： Hiroaki Murakami ,  Osamu Takahashi ,  Jieming Qi

IPC: H03K19/20

CPC classification number: H03K19/1737 ,  H03K19/0016

Abstract: Systems and methods for reducing the power consumption of some combinations of logic gates by reducing the number of unnecessary transitions that are made by logic gates that do not affect the output of the logic. In one embodiment, a modified exclusive-OR (XOR) gate is coupled to a modified multiplexer. The XOR gate has two inputs, Ain and Bin, and an output, XORout, which is provided as an input to the multiplexer. Another input to the multiplexer is Cin. A select signal is input to the multiplexer to select either Cin or XORout to be provided at the output of the multiplexer. If XORout is selected, the XOR gate operates in a first mode in which it functions as a normal XOR gate. If Cin is selected, the XOR gate operates in a second mode in which the XOR gate uses less power than when the XOR gate operates normally.

Abstract translation: 通过减少不影响逻辑输出的逻辑门进行的不必要的转换次数来减少逻辑门的某些组合的功耗的系统和方法。 在一个实施例中，修改的异或（XOR）门耦合到修改的多路复用器。 XOR门具有两个输入，即中的和B _{中的A 和作为多路复用器的输入提供的输出XOR < 。 复用器的另一个输入是中的C 。 选择信号被输入到多路复用器以选择要在多路复用器的输出处提供的或XOR 输出中的C 。 如果选择XOR ，则异或门以第一模式工作，其中它用作正常的异或门。 如果选择了中的C ，则异或门以第二模式工作，其中XOR门比XOR门正常工作时使用的功率更小。}

公开(公告)号：US06973010B1

公开(公告)日：2005-12-06

申请号：US09830519

申请日：2000-08-23

Applicant: Nobuhiro Koike ,  Mamoru Miyasaka ,  Osamu Takahashi

Inventor： Nobuhiro Koike ,  Mamoru Miyasaka ,  Osamu Takahashi

IPC: G04C3/00 ,  G04C10/00 ,  G04C13/11 ,  H02K3/18 ,  H02K37/16 ,  H02K37/00

CPC classification number: G04C13/11 ,  G04C3/008 ,  G04C10/00 ,  H02K3/18 ,  H02K37/16

Abstract: In a generator 120 in an electronic-controlled mechanical timepiece, the winding core 133b of a coil 134 arranged nearer to the perimeter of a base plate 2 is made shorter than the winding core 123b of a coil 124 arranged more inside. Accordingly, it is possible to make the area of an opening 2c can be made smaller in comparison with the prior art, and make the timepiece more small-sized by making smaller the outer diameter of the base plate 2 as keeping the distance D1 between the corner part of the opening 2c and the perimeter of the base plate 2 to the same degree as the prior art and thereby securing the strength of the base plate 2.

Abstract translation: 在电子机械钟表的发电机120中，布置得更靠近基板2的周边的线圈134的卷绕芯133b比布置在内侧的线圈124的卷绕芯123b短。 因此，与现有技术相比，可以使开口部2c的面积变小，通过使基板2的外径保持距离D 1更小，使钟表体积更小 在开口部2c的角部与基板2的周边之间，与现有技术的程度相同，由此确保基板2的强度。

公开(公告)号：US20050264322A1

公开(公告)日：2005-12-01

申请号：US10852868

申请日：2004-05-25

Applicant: Takaaki Nakazato ,  Toru Asano ,  Osamu Takahashi ,  Sang Dhong

Inventor： Takaaki Nakazato ,  Toru Asano ,  Osamu Takahashi ,  Sang Dhong

IPC: G11C11/419 ,  G11C7/06 ,  G11C7/12 ,  H03F3/45 ,  H03K3/356 ,  H03K19/0948

CPC classification number: G11C7/065 ,  G11C7/12 ,  H03F3/45183 ,  H03F2203/45318

Abstract: Systems and methods for pre-charging opposing nodes in a sense amplifier to substantially the same voltage in order to reduce or eliminate malfunctions arising from differences in threshold voltages of transistors coupled to the opposing nodes. One embodiment is a method including providing a silicon-on-insulator (SOI) sense amplifier having intermediate nodes between the transistors coupling each output data line to the corresponding input bit line and pre-charging each intermediate node to a predetermined voltage while the sense amplifier is not enabled. In one embodiment, the intermediate nodes are pre-charged by coupling them to a voltage source through pre-charge paths that do not include the data line pull-down transistors. In one embodiment, the method also includes decoupling the pre-charge paths after pre-charging the intermediate nodes and then enabling the sense amplifier.

Abstract translation: 用于将读出放大器中的相对节点预充电到基本相同的电压的系统和方法，以便减少或消除由耦合到相对节点的晶体管的阈值电压的差异引起的故障。 一个实施例是一种方法，包括提供绝缘体上硅（SOI）读出放大器，该晶体管在晶体管之间具有中间节点，每个晶体管将每个输出数据线耦合到相应的输入位线，并将每个中间节点预充电到预定电压，而读出放大器 未启用 在一个实施例中，中间节点通过不包括数据线下拉晶体管的预充电路径将其耦合到电压源进行预充电。 在一个实施例中，该方法还包括在对中间节点预充电然后启用读出放大器之后去耦合预充电路径。

公开(公告)号：US20050261395A1

公开(公告)日：2005-11-24

申请号：US11125406

申请日：2005-05-10

Applicant: Takahiro Ishizuka ,  Toshiki Fujiwara ,  Osamu Takahashi ,  Junichi Yamanouchi ,  Yoshiharu Yabuki

Inventor： Takahiro Ishizuka ,  Toshiki Fujiwara ,  Osamu Takahashi ,  Junichi Yamanouchi ,  Yoshiharu Yabuki

IPC: C09D11/00 ,  C03C17/00

CPC classification number: C09D11/32

Abstract: To provide an ink composition that when printed using a nozzle, does not cause clogging at the chip of the nozzle, is free from paper dependency, and when printed on an arbitrarily chosen paper, exhibits superior properties in water resistance, scratch resistance, lightfastness and ozone resistance and an inkjet recording method using it. The ink composition contains colored fine particles containing an oil-soluble polymer and an oil-soluble dye having an oxidation potential higher than 1.0 V (vs SCE), in an aqueous medium.

Abstract translation: 为了提供当使用喷嘴打印时不会在喷嘴的芯片处产生堵塞的油墨组合物，没有纸张依赖性，并且当印刷在任意选择的纸张上时，在耐水性，耐刮擦性，耐光性和 耐臭氧性和使用它的喷墨记录方法。 油墨组合物含有在水性介质中含有油溶性聚合物和氧化电位高于1.0V（相对于SCE）的油溶性染料的着色微粒。

公开(公告)号：US06957714B2

公开(公告)日：2005-10-25

申请号：US10617784

申请日：2003-07-14

Applicant: Osamu Takahashi ,  Ryo Ishiyama

Inventor： Osamu Takahashi ,  Ryo Ishiyama

IPC: H04R7/18 ,  H04R7/02 ,  H04R7/20 ,  G10K13/00 ,  H04R7/14 ,  H04R7/16 ,  H04R9/04

CPC classification number: H04R7/20 ,  H04R2307/201 ,  H04R2307/207 ,  H04R2499/13

Abstract: The speaker has a diaphragm main body 30 supported resiliently on a frame 23 via an edge portion 31 around its outer circumference, and the groove ribs 35 integrally formed in the edge portion 31, wherein a regulation member 37 for partially improving a flexural strength of the edge portion 31 is provided on a part of the front or back face of the edge portion 31.

Abstract translation: 扬声器具有通过围绕其外周的边缘部分31弹性地支撑在框架23上的隔膜主体30和一体地形成在边缘部分31中的槽肋35，其中，用于部分地提高弯曲强度的调节构件37 边缘部分31设置在边缘部分31的正面或背面的一部分上。

公开(公告)号：US20050142674A1

公开(公告)日：2005-06-30

申请号：US11062615

申请日：2005-02-22

Applicant: Osamu Takahashi ,  Kunio Ogasawara

Inventor： Osamu Takahashi ,  Kunio Ogasawara

IPC: H01L21/8247 ,  C02F9/00 ,  H01L21/304 ,  H01L21/306 ,  H01L21/8234 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  B01D61/02

CPC classification number: C02F9/00 ,  C02F1/001 ,  C02F1/32 ,  C02F1/42 ,  C02F1/441 ,  C02F1/444 ,  C02F2103/04 ,  H01L21/02057 ,  H01L21/02063 ,  H01L21/28238 ,  H01L21/28273 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11546

Abstract: Provided is a fabrication method of a semiconductor integrated circuit device, which comprises disposing, in a ultrapure water preparing system, UF equipment having therein a UF module which has been manufactured by disposing, in a body thereof, a plurality of capillary hollow fiber membranes composed of a polysulfone membrane or polyimide membrane, bonding the plurality of hollow fiber membranes at end portions thereof by hot welding, and by this hot welding, simultaneously adhering the hollow fiber membranes to the body. Upon preparation of ultrapure water to be used for the fabrication of the semiconductor integrated circuit device, the present invention makes it possible to prevent run-off of ionized amine into the ultrapure water.

Abstract translation: 本发明提供一种半导体集成电路器件的制造方法，其特征在于，在超纯水制备系统中，设置有UF器件，UF器件具有UF模块，所述UF模块通过在其主体中配置多个毛细管中空纤维膜而制造， 的聚砜膜或聚酰亚胺膜，通过热熔接在多个中空纤维膜的端部粘接多个中空纤维膜，并且通过该热焊接，同时将中空纤维膜粘附到体上。 在制备用于制造半导体集成电路器件的超纯水时，本发明可以防止离子化胺流入超纯水中。

公开(公告)号：US06898135B2

公开(公告)日：2005-05-24

申请号：US10606587

申请日：2003-06-26

Applicant: Toru Asano ,  Sang Hoo Dhong ,  Takaaki Nakazato ,  Osamu Takahashi

Inventor： Toru Asano ,  Sang Hoo Dhong ,  Takaaki Nakazato ,  Osamu Takahashi

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/00

CPC classification number: G11C7/1069 ,  G11C7/065 ,  G11C7/1051

Abstract: Disclosed is an apparatus for and a method of overcoming signal delay problems in a read-out path occurring in connection with pipelined memory circuits. A latch type sense amplifier (SA) is used to receive the memory cell logic levels during a pre-charge state in a cycle prior to read-out. Thus, the SA may quickly provide an output signal during a read latch clock cycle. The SA output is passed through a dynamically enabled logic circuit to a latch circuit for holding the receiving logic value for use in the next clock cycle.

Abstract translation: 公开了一种克服与流水线存储器电路相关的读出路径中的信号延迟问题的装置和方法。 闩锁型读出放大器（SA）用于在读出之前的一个周期中的预充电状态期间接收存储单元逻辑电平。 因此，SA可以在读取锁存时钟周期期间快速提供输出信号。 SA输出通过一个动态使能的逻辑电路被传送到一个锁存电路，用于保持接收逻辑值用于下一个时钟周期。