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    Nonvolatile memory using flexible erasing methods and method and system for using same
    33.
    发明授权
    Nonvolatile memory using flexible erasing methods and method and system for using same 有权
    非易失性存储器采用灵活的擦除方法和方法及系统使用

    公开(公告)号：US06411546B1

    公开(公告)日：2002-06-25

    申请号：US09565517

    申请日：2000-05-05

    Applicant: Petro Estakhri ,  Siamack Nemazie ,  Mahmud Assar ,  Parviz Keshtbod

    Inventor： Petro Estakhri ,  Siamack Nemazie ,  Mahmud Assar ,  Parviz Keshtbod

    IPC: G11C1604

    CPC classification number: G11C16/102 ,  G06F3/0604 ,  G06F3/0607 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0679 ,  G06F11/1068 ,  G06F12/0246 ,  G11C8/12 ,  G11C16/08

    Abstract: An embodiment of the present invention is disclosed to include a nonvolatile memory system for controlling erase operations performed on a nonvolatile memory array comprised of rows and columns, the nonvolatile memory array stores digital information organized into blocks with each block having one or more sectors of information and each sector having a user data field and an extension field and each sector stored within a row of the memory array. A controller circuit is coupled to a host circuit and is operative to perform erase operations on the nonvolatile memory array, the controller circuit erases an identified sector of information having a particular user data field and a particular extension field wherein the particular user field and the particular extension field are caused to be erased separately.

    Abstract translation: 公开了本发明的实施例，其包括用于控制对由行和列组成的非易失性存储器阵列执行的擦除操作的非易失性存储器系统，非易失性存储器阵列存储组织成块的数字信息，每个块具有一个或多个信息扇区 并且每个扇区具有用户数据字段和扩展字段，并且每个扇区存储在存储器阵列的行内。 控制器电路耦合到主机电路并且可操作以对非易失性存储器阵列执行擦除操作，控制器电路擦除所识别的具有特定用户数据字段和特定扩展字段的信息扇区，其中特定用户字段和特定用户字段 扩展字段被分别擦除。

    Spacer flash cell device with vertically oriented floating gate
    34.
    发明授权
    Spacer flash cell device with vertically oriented floating gate 失效
    具有垂直定向浮动栅极的隔板闪存单元

    公开(公告)号：US5479368A

    公开(公告)日：1995-12-26

    申请号：US129866

    申请日：1993-09-30

    Applicant: Parviz Keshtbod

    Inventor： Parviz Keshtbod

    IPC: H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  G11C16/04

    CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/4232 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883

    Abstract: A flash EPROM cell has a reduced cell size by providing vertical coupling between the floating gate and the bit line during programming. The erase operation is done by tunneling of electrons from the sharp tip of the Poly spacer to the control gate. The cell is adapted so that the source for each cell within the array is the source of an adjacent cell and the drain is the drain to another adjacent cell. The cell is formed by forming the drain regions into the substrate through openings in a first insulator that is preferably the field oxide. A second insulator is deposited over the first insulator, over the substrate and along the side walls of the openings and is preferably a thin layer so that the opening is covered with a thin insulating layer. The insulated opening is filled with a first doped polysilicon layer. The field oxide is selectively removed. A gate oxide is grown and a second polysilicon layer is formed and then etched to form spacers along the edges of the first polysilicon/second insulator structure. The second polysilicon is selectively etched and a tunneling insulator layer is formed thereover. A third polysilicon layer is formed over the tunneling insulator.

    Abstract translation: 闪存EPROM单元在编程期间通过在浮动栅极和位线之间提供垂直耦合而具有减小的单元尺寸。 擦除操作是通过将电子从Poly间隔物的尖端引导到控制栅极进行的。 单元被适配成使得阵列内的每个单元的源极是相邻单元的源极，漏极是另一相邻单元的漏极。 通过在优选为场氧化物的第一绝缘体中的开口将漏区形成为衬底而形成电池。 第二绝缘体沉积在第一绝缘体上方，在衬底上并且沿着开口的侧壁，并且优选地是薄层，使得开口被薄绝缘层覆盖。 绝缘开口填充有第一掺杂多晶硅层。 有选择地去除场氧化物。 生长栅极氧化物并形成第二多晶硅层，然后蚀刻以沿着第一多晶硅/第二绝缘体结构的边缘形成间隔物。 选择性地蚀刻第二多晶硅，并在其上形成隧穿绝缘体层。 在隧道绝缘体上形成第三多晶硅层。

    Method for manufacturing high density non-volatile magnetic memory
    35.
    发明授权
    Method for manufacturing high density non-volatile magnetic memory 有权
    高密度非挥发性磁记忆体的制造方法

    公开(公告)号：US08802451B2

    公开(公告)日：2014-08-12

    申请号：US13610587

    申请日：2012-09-11

    Applicant: Roger Klas Malmhall ,  Kimihiro Satoh ,  Jing Zhang ,  Parviz Keshtbod ,  Rajiv Yadav Ranjan

    Inventor： Roger Klas Malmhall ,  Kimihiro Satoh ,  Jing Zhang ,  Parviz Keshtbod ,  Rajiv Yadav Ranjan

    IPC: H01L21/00

    CPC classification number: H01L43/12 ,  B82Y10/00 ,  B82Y25/00 ,  G11C11/161 ,  H01L27/228

    Abstract: Methods of fabricating MTJ arrays using two orthogonal line patterning steps are described. Embodiments are described that use a self-aligned double patterning method for one or both orthogonal line patterning steps to achieve dense arrays of MTJs with feature dimensions one half of the minimum photo lithography feature size (F). In one set of embodiments, the materials and thicknesses of the stack of layers that provide the masking function are selected so that after the initial set of mask pads have been patterned, a sequence of etching steps progressively transfers the mask pad shape through the multiple mask layer and down through all of the MTJ cell layers to the form the complete MTJ pillars. In another set of embodiments, the MTJ/BE stack is patterned into parallel lines before the top electrode layer is deposited.

    Abstract translation: 描述使用两个正交线图案化步骤制造MTJ阵列的方法。 描述了使用用于一个或两个正交线图案化步骤的自对准双图案化方法来实现特征尺寸为最小光刻特征尺寸（F）的一半的MTJ的致密阵列的实施例。 在一组实施例中，选择提供掩模功能的层叠层的材料和厚度，使得在初始掩模焊盘组被图案化之后，一系列蚀刻步骤逐渐地将掩模焊盘形状传递通过多个掩模 通过所有的MTJ单元层的层和下层形成完整的MTJ柱。 在另一组实施例中，在沉积顶部电极层之前，将MTJ / BE叠层图案化成平行线。

    MRAM etching processes
    36.
    发明授权
    MRAM etching processes 有权

    公开(公告)号：US08536063B2

    公开(公告)日：2013-09-17

    申请号：US13199490

    申请日：2011-08-30

    Applicant: Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang ,  Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger K. Malmhall

    Inventor： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang ,  Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger K. Malmhall

    IPC: H01L21/302 ,  H01L21/461

    CPC classification number: H01L43/12 ,  H01L29/00

    Abstract: Various embodiments of the invention relate to etching processes used in fabrication of MTJ cells in an MRAM device. The various embodiments can be used in combination with each other. The first embodiment adds a hard mask buffer layer between a hard mask and a top electrode. The second embodiment uses a multilayered etching hard mask. The third embodiment uses a multilayered top electrode structure including a first Cu layer under a second layer such as Ta. The fourth embodiment is a two-phase etching process used for the bottom electrode to remove re-deposited material while maintaining a more vertical sidewall etching profile. In the first phase the bottom electrode layer is removed using carbonaceous reactive ion etching until the endpoint. In the second phase an inert gas and/or oxygen plasma is used to remove the polymer that was deposited during the previous etching processes.

    Method for manufacturing non-volatile magnetic memory
    37.
    发明授权
    Method for manufacturing non-volatile magnetic memory 有权
    制造非易失性磁记忆体的方法

    公开(公告)号：US08535952B2

    公开(公告)日：2013-09-17

    申请号：US12040827

    申请日：2008-02-29

    Applicant: Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

    Inventor： Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

    IPC: H01L21/00

    CPC classification number: H01L43/12 ,  B82Y10/00 ,  B82Y25/00 ,  G11C11/16 ,  H01L27/228

    Abstract: In accordance with a method of the present invention, a method of manufacturing a magnetic random access memory (MRAM) cell and a corresponding structure thereof are disclosed to include a multi-stage manufacturing process. The multi-stage manufacturing process includes performing a front end on-line (FEOL) stage to manufacture logic and non-magnetic portions of the memory cell by forming an intermediate interlayer dielectric (ILD) layer, forming intermediate metal pillars embedded in the intermediate ILD layer, depositing a conductive metal cap on top of the intermediate ILD layer and the metal pillars, performing magnetic fabrication stage to make a magnetic material portion of the memory cell being manufactured, and performing back end on-line (BEOL) stage to make metal and contacts of the memory cell being manufactured.

    Abstract translation: 根据本发明的方法，公开了一种制造磁随机存取存储器（MRAM）单元及其相应结构的方法，以包括多级制造工艺。 多级制造过程包括通过形成中间层间电介质（ILD）层来形成前端在线（FEOL）级来制造存储单元的逻辑和非磁性部分，形成嵌入在中间ILD中的中间金属柱 层，在中间ILD层和金属柱的顶部上沉积导电金属帽，进行磁性制造阶段以制造存储单元的磁性材料部分，并执行后端在线（BEOL）阶段以制造金属 和正在制造的存储单元的触点。

    Non-volatile perpendicular magnetic memory with low switching current and high thermal stability
    40.
    发明授权
    Non-volatile perpendicular magnetic memory with low switching current and high thermal stability 有权
    具有低开关电流和高热稳定性的非易失性垂直磁存储器

    公开(公告)号：US08493777B2

    公开(公告)日：2013-07-23

    申请号：US13453940

    申请日：2012-04-23

    Applicant: Rajiv Yadav Ranjan ,  Parviz Keshtbod

    Inventor： Rajiv Yadav Ranjan ,  Parviz Keshtbod

    IPC: G11C11/14

    CPC classification number: H01L43/10 ,  B82Y10/00 ,  G11C11/161 ,  G11C11/1675 ,  H01L27/228

    Abstract: A non-volatile current-switching magnetic memory element includes a bottom electrode, a pinning layer formed on top of the bottom electrode, and a fixed layer formed on top of the pinning layer. The non-volatile current-switching magnetic memory element further includes a tunnel layer formed on top of the pinning layer, a first free layer with a perpendicular anisotropy that is formed on top of the tunnel layer, a granular film layer formed on top of the free layer, a second free layer formed on top of the granular film layer, a cap layer formed on top of the second layer, and a top electrode formed on top of the cap layer.

    Abstract translation: 非易失性电流切换磁存储元件包括底电极，形成在底电极顶部的钉扎层和形成在钉扎层顶部上的固定层。 非易失性电流切换磁存储元件还包括形成在钉扎层顶部的隧道层，形成在隧道层顶部上的具有垂直各向异性的第一自由层，形成在隧道层顶部的粒状膜层 自由层，形成在所述粒状膜层的顶部上的第二自由层，形成在所述第二层的顶部上的盖层，以及形成在所述盖层的顶部上的顶部电极。

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