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公开(公告)号:US20230326885A1
公开(公告)日:2023-10-12
申请号:US18210392
申请日:2023-06-15
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Pascal FORNARA
IPC: H01L23/62 , H01H85/02 , H01L23/525 , H01L21/66
CPC classification number: H01L23/62 , H01H85/0241 , H01L23/5256 , H01L22/34 , H01H2085/0283
Abstract: A semiconductor wafer includes first zones containing integrated circuits, each first zone including a substrate and a sealing ring at a periphery of the substrate. The first zones are separated from each other by second zones defining cutting lines or paths. The integrated circuit includes an electrically conductive fuse that extends between a first location inside the integrated circuit and a second location situated outside the integrated circuit beyond one of the cutting lines. This electrically conductive fuse includes a portion that passes through the sealing ring and another portion that straddles the adjacent cutting line. The portion of the fuse that passes through is electrically isolated from the sealing ring and from the substrate. The straddling portion is configured to be sliced, when cutting the wafer along the cutting line, so as to cause the fuse to change from an electrical on state to an electrical off state.
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公开(公告)号:US11784567B2
公开(公告)日:2023-10-10
申请号:US17571741
申请日:2022-01-10
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Sebastien Ortet
Abstract: In an embodiment, a device includes a switching power supply configured to have a first operating mode synchronized by a first clock signal generated by a clock generator a second asynchronous operating mode. The clock generator is configured such that the first clock signal becomes equal, upon transition from the second operating mode to the first operating mode, to the signal having the closest rising edge of a second clock signal and a third clock signal complementary to the second clock signal.
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公开(公告)号:US20230318589A1
公开(公告)日:2023-10-05
申请号:US18127397
申请日:2023-03-28
Inventor: Giulio ZOPPI , Vincent Pascal ONDE , Giuseppe ROMANO
IPC: H03K5/1254 , G01D5/347 , H03K3/013
CPC classification number: H03K5/1254 , G01D5/3473 , H03K3/013
Abstract: A first input node receives a first input signal and a second input node receives a second input signal. The first and second input signals are in phase quadrature. An edge detector circuit senses the first input signal and produces a pulsed signal indicative of edges detected in the first input signal. A pulse skip and reset circuit senses the pulsed signal and the second input signal, and produces a reset signal indicative of pulses detected in the pulsed signal while the second input signal is de-asserted. A sampling circuit senses the second input signal and the reset signal, and produces an output signal that is deasserted in response to assertion of the second input signal and is asserted in response to a pulse being detected in the reset signal.
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公开(公告)号:US20230317637A1
公开(公告)日:2023-10-05
申请号:US18206923
申请日:2023-06-07
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Pascal FORNARA , Fabrice MARINET
IPC: H01L23/00 , H01L29/788 , G06F21/75 , G06F21/79 , H01L23/522 , H10B41/35
CPC classification number: H01L23/573 , H01L29/7883 , H01L23/576 , G06F21/75 , G06F21/79 , H01L23/5223 , H10B41/35 , G06F21/87
Abstract: An integrated circuit memory includes a state transistor having a floating gate which stores a respective data value. A device for protecting the data stored in the memory includes a capacitive structure having a first electrically-conducting body coupled to the floating gate of the state transistor, a dielectric body, and a second electrically-conducting body coupled to a ground terminal. The dielectric body is configured, if an aqueous solution is brought into contact with the dielectric body, to electrically couple the floating gate and the ground terminal so as to modify the charge on the floating gate and to lose the corresponding data. Otherwise, the dielectric body is configured to electrically isolate the floating gate and the ground terminal.
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公开(公告)号:US20230300919A1
公开(公告)日:2023-09-21
申请号:US18119626
申请日:2023-03-09
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Philippe ALARY
Abstract: A first near-field communication device is remotely powered by a second near-field communication device. The first near-field communication device receives from the second near-field communication device a frame indicating a failure of a data reception by the second near-field communication device. In response, at least one transmission parameter of the first near-field communication device is modified prior to another attempt of transmission of the data.
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公开(公告)号:US11764731B2
公开(公告)日:2023-09-19
申请号:US18059812
申请日:2022-11-29
Applicant: STMicroelectronics (Alps) SAS , STMicroelectronics (Grenoble 2) SAS , STMicroelectronics (Rousset) SAS , STMicroelectronics S.r.l.
CPC classification number: H03B5/36 , G06F1/10 , H03F3/245 , H04B1/0475 , H03B2200/004 , H03F2200/451 , H04B2001/0408
Abstract: The present disclosure relates to an electronic device comprising a first capacitor and a quartz crystal coupled in series between a first node and a second node; an inverter coupled between the first and second nodes; a first variable capacitor coupled between the first node and a third node; and a second variable capacitor coupled between the second node and the third node.
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公开(公告)号:US20230282286A1
公开(公告)日:2023-09-07
申请号:US18173472
申请日:2023-02-23
Inventor: Francesco La Rosa , Marco Bildgen
Abstract: An integrated circuit comprises a memory device including a memory plane having non-volatile memory cells and being non-observable in read mode from outside the memory device, a controller, internal to the memory device, configured to detect the memorized content of the memory plane, and when the memorized content contains locking content, automatically lock any access to the memory plane from outside the memory device, the integrated circuit then being in a locked status, and authorize delivery outside the memory device of at least one sensitive datum stored in the memory plane.
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公开(公告)号:US11722872B2
公开(公告)日:2023-08-08
申请号:US17478399
申请日:2021-09-17
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Alexandre Tramoni
CPC classification number: H04W4/80 , H02J50/10 , H02J50/80 , H04B5/0025
Abstract: A method includes detecting, by a first near-field communication device, the presence of a second near-field communication device. In a case where the second device is intended to be charged in near-field by the first device, the method further includes adjusting, by a control device, an impedance of an impedance matching circuit forming part of a near-field communication circuit of the first device.
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公开(公告)号:US11715093B2
公开(公告)日:2023-08-01
申请号:US17127269
申请日:2020-12-18
Inventor: Olivier Van Nieuwenhuyze , Jean-Marc Grimaud
IPC: H04L41/0803 , G06Q20/32 , G06K7/10 , H04L69/329
CPC classification number: G06Q20/3278 , G06K7/10297 , H04L41/0803 , H04L69/329
Abstract: A method of configuring a contactless communication device is provided. The contactless communication device includes integrated circuits hosting at least two applications compatible with the same communication protocols or compatible with the same communication protocol and using different communication parameters and a contactless communication circuit. The method includes detecting, by the contactless communication circuit, an interruption of a transaction initiated by a proximity coupling reader.
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公开(公告)号:US20230223448A1
公开(公告)日:2023-07-13
申请号:US18094023
申请日:2023-01-06
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Pascal FORNARA , Christian RIVERO , Franck JULIEN
IPC: H01L29/40 , H01L29/45 , H01L21/768 , H01L23/532
CPC classification number: H01L29/401 , H01L29/456 , H01L21/76843 , H01L21/76858 , H01L23/53266 , H01L23/5226
Abstract: A method of manufacturing a radio frequency switch includes the steps of: forming a first silicide layer on a second conductive or semiconductor layer; forming a third insulating layer on the first layer; forming a cavity in the third insulating layer reaching the first silicide layer; forming a fourth metal layer in the cavity in contact with the first silicide layer; performing a non-oxidizing annealing; and filling the cavity with a conductive material. The first silicide layer is provided on one or more of the gate, source, and drain of a transistor forming the radio frequency switch.
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