公开(公告)号：US20120285733A1

公开(公告)日：2012-11-15

申请号：US13263359

申请日：2010-04-08

申请人： Takahiko Kato ,  Takashi Naito ,  Hiroki Yamamoto ,  Takuya Aoyagi ,  Seiichi Watanabe ,  Seiji Miura ,  Norihito Sakaguchi ,  Kazuki Aoshima ,  Kenji Ohkubo

发明人： Takahiko Kato ,  Takashi Naito ,  Hiroki Yamamoto ,  Takuya Aoyagi ,  Seiichi Watanabe ,  Seiji Miura ,  Norihito Sakaguchi ,  Kazuki Aoshima ,  Kenji Ohkubo

IPC分类号： H01B1/02 ,  H05K1/09 ,  H01B5/00

CPC分类号： C22C9/01 ,  C22C9/06 ,  H01J1/02 ,  H01J2211/225 ,  H01L31/022425 ,  H05K1/092 ,  Y02E10/50

摘要： An object of the present invention is to provide an electronic component using a Cu-based conductive material that can suppress oxidization even in a heat treatment in an oxidizing atmosphere and that can suppress an increase in an electrical resistance. In an electronic component having an electrode or a wiring, a ternary alloy made from three elements consisting of Cu, Al, and Co is used as a Cu-based wiring material that can prevent oxidization of the electrode or the wiring. Specifically, part or the whole of the electrode or the wiring has a chemical composition in which an Al content is 10 at % to 25 at %, a Co content is 5 at % to 20 at %, and the balance is composed of Cu and unavoidable impurities, and the chemical composition represents a ternary alloy in which two phases of a Cu solid solution formed by Al and Co being dissolved into Cu and a CoAl intermetallic compound coexist together.

摘要翻译： 本发明的目的是提供一种使用Cu基导电材料的电子部件，即使在氧化气氛中的热处理中也能够抑制氧化，并且能够抑制电阻的增加。 在具有电极或布线的电子部件中，使用由Cu，Al和Co组成的三个元素制成的三元合金作为能够防止电极或布线的氧化的Cu系布线材料。 具体地说，电极或布线的一部分或全部具有Al含量为10原子％至25原子％的Co化学组成，Co含量为5原子％至20原子％，余量由Cu和 不可避免的杂质，化学组成表示三元合金，其中由Al和Co形成的Cu固溶体中的两相溶解于Cu和CoAl金属间化合物共存。

公开(公告)号：US20120054421A1

公开(公告)日：2012-03-01

申请号：US13197296

申请日：2011-08-03

申请人： Yukie HIRATSUKA ,  Seiji MIURA ,  Yukihide INAGAKI

发明人： Yukie HIRATSUKA ,  Seiji MIURA ,  Yukihide INAGAKI

IPC分类号： G06F12/00

CPC分类号： G06F3/0613 ,  G06F3/0625 ,  G06F3/0679 ,  G06F3/068 ,  G06F12/0246 ,  G06F12/0802 ,  G06F2212/222 ,  G06F2212/7201 ,  G06F2212/7211 ,  Y02D10/13

摘要： A read cache and a write cache are made up of two kinds of nonvolatile memories whose characteristics are different. For example, nonvolatile memory whose write endurance is high is assigned to the write cache, nonvolatile memory whose write endurance is low is assigned to the read cache, and the management tables of data in these caches are stored in the nonvolatile memory whose write endurance is high. Alternatively, nonvolatile memory that has a fast write speed but has a slow read speed is adopted for the write cache and nonvolatile memory that has a fast read speed but has a slow write speed is adopted for the read cache.

摘要翻译： 读取高速缓存和写入高速缓存由特性不同的两种非易失性存储器组成。 例如，写入耐久性高的非易失性存储器被分配给写入高速缓存，写入耐受性低的非易失性存储器被分配给读取高速缓存，并且这些高速缓存中的数据的管理表被存储在写入耐久性为 高。 或者，对于写入高速缓冲存储器采用具有快速写入速度但具有较慢读取速度的非易失性存储器，并且对于读取高速缓存采用具有快速读取速度但具有较慢写入速度的非易失性存储器。

公开(公告)号：US20110319399A1

公开(公告)日：2011-12-29

申请号：US13255817

申请日：2010-03-11

申请人： Seiji Miura ,  Tsutomu Awamura ,  Yuhiro Yamazaki ,  Hironari Fujii

发明人： Seiji Miura ,  Tsutomu Awamura ,  Yuhiro Yamazaki ,  Hironari Fujii

IPC分类号： A61K31/5415 ,  A61K31/405 ,  A61P29/00 ,  A61K31/196 ,  A61K31/365 ,  A61K31/415 ,  A61K31/192 ,  A61K31/407

CPC分类号： A61K31/16 ,  A61K9/7053 ,  A61K31/196 ,  A61K45/06 ,  A61K2300/00

摘要： An external preparation containing the following components (A) and (B): (A) a non-steroidal analgesic/anti-inflammatory agent, and (B) an organic amine. The external preparation of the present invention has improved skin permeation and excellent stability of a non-steroidal analgesic/anti-inflammatory agent in the external preparation. The external preparation of the present invention also has excellent appearance.

摘要翻译： 含有以下组分（A）和（B）的外用制剂：（A）非甾体镇痛/抗炎剂，和（B）有机胺。 本发明的外用制剂改善了外用制剂中非甾体止痛/抗炎剂的皮肤渗透性和优异的稳定性。 本发明的外用制剂也具有优异的外观。

公开(公告)号：US20110258373A1

公开(公告)日：2011-10-20

申请号：US13169912

申请日：2011-06-27

申请人： Seiji MIURA ,  Kazushige Ayukawa

发明人： Seiji MIURA ,  Kazushige Ayukawa

IPC分类号： G06F12/02 ,  G06F12/06

CPC分类号： G11C11/005 ,  G06F12/0638 ,  G06F2212/2022 ,  G11C7/20 ,  G11C11/4072 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2924/00014

摘要： A memory system including ROM and RAM in which reading and writing are enabled. A memory system includes a non-volatile memory (FLASH), DRAM, a control circuit, and an information processing device. Data in FLASH is transferred to SRAM or DRAM in advance. Data transfer between the non-volatile memory and the DRAM can be performed in the background. The memory system including these plural chips is configured as a memory system module in which each chip is mutually laminated and each chip is wired via a ball grid array (BGA) and bonding wire between the chips. Data in FLASH can be read at the similar speed to that of DRAM by securing a region in which the data in FLASH can be copied in DRAM and transferring the data to DRAM in advance immediately after power is turned on or by a load instruction.

摘要翻译： 包括ROM和RAM的存储器系统，其中启用读和写。 存储器系统包括非易失性存储器（FLASH），DRAM，控制电路和信息处理设备。 预先将FLASH中的数据传送到SRAM或DRAM。 在非易失性存储器和DRAM之间的数据传输可以在后台执行。 包括这些多个芯片的存储器系统被配置为存储器系统模块，其中每个芯片相互层叠，并且每个芯片经由球栅阵列（BGA）和芯片之间的接合线布线。 FLASH中的数据可以通过保护FLASH中的数据可以在DRAM中复制的区域以及在接通电源或通过加载指令之后将数据传送到DRAM中，以与DRAM类似的速度读取速度。

公开(公告)号：US08028119B2

公开(公告)日：2011-09-27

申请号：US11435712

申请日：2006-05-18

申请人： Seiji Miura

发明人： Seiji Miura

IPC分类号： G06F13/38 ,  G06F12/00 ,  G08C25/00

CPC分类号： G06F12/0246 ,  G06F11/1068 ,  G06F12/0862 ,  G06F12/0888 ,  G06F12/0893 ,  G06F2212/2022 ,  G11C5/02 ,  G11C7/1006 ,  G11C2207/2245 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： A memory system including a non-volatile memory, a cache memory, a control circuit, and a data processing device is configured. The high speed can be achieved by transferring data in the non-volatile memory to the cache memory to retain the same therein. When the data in the non-volatile memory is transferred to the cache memory, error correction is performed so as to improve the reliability. Since the cache memory and the non-volatile memory can be accessed from the data processing device independently, improvement in usability can be achieved. The memory system including the plurality of chips is configured as a memory system module where respective chips are arranged in a stacked manner and wired by a ball grid array (BGA) and wire bonding between chips.

摘要翻译： 配置包括非易失性存储器，高速缓冲存储器，控制电路和数据处理装置的存储器系统。 可以通过将非易失性存储器中的数据传送到高速缓冲存储器来保持高速度来实现高速度。 当非易失性存储器中的数据被传送到高速缓冲存储器时，执行错误校正以提高可靠性。 由于可以独立于数据处理装置访问高速缓冲存储器和非易失性存储器，所以可以实现可用性的提高。 包括多个芯片的存储器系统被配置为存储器系统模块，其中各个芯片以堆叠的方式布置并且由球栅阵列（BGA）布线并且在芯片之间引线接合。

公开(公告)号：US08024512B2

公开(公告)日：2011-09-20

申请号：US12620912

申请日：2009-11-18

申请人： Seiji Miura ,  Kazushige Ayukawa

发明人： Seiji Miura ,  Kazushige Ayukawa

IPC分类号： G06F12/00

CPC分类号： G06F13/161 ,  G06F12/0215 ,  G11C7/1018 ,  Y02D10/13 ,  Y02D10/14

摘要： A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.

摘要翻译： 存储器控制器和数据处理器响应于连续访问不同页面的事件，将其操作模式从用于高速访问的页面模式切换到同一页面到页面关闭模式，从而执行存储器访问 在高速和低功耗下。

公开(公告)号：US07994451B2

公开(公告)日：2011-08-09

申请号：US11290988

申请日：2005-12-01

申请人： Koichi Shigematsu ,  Seiji Miura

发明人： Koichi Shigematsu ,  Seiji Miura

IPC分类号： H01L21/46 ,  H01L21/02

CPC分类号： H01L21/67253 ,  B23K26/0853 ,  B23K26/0869 ,  B23K2101/40 ,  H01L21/67092

摘要： A laser beam processing machine comprising a chuck table for holding a workpiece, a laser beam application means for applying a pulse laser beam to the workpiece held on the chuck table, and a processing-feed means for processing-feeding the chuck table and the laser beam application means relative to each other, wherein the machine further comprises a feed amount detection means for detecting the processing-feed amount of the chuck table and a control means for controlling the laser beam application means based on a detection signal from the feed amount detection means, and the control means outputs an application signal to the laser beam application means for each predetermined processing-feed amount based on a signal from the feed amount detection means.

摘要翻译： 一种激光束处理机，包括用于保持工件的卡盘台，用于将脉冲激光束施加到夹持在卡盘台上的工件的激光束施加装置，以及用于加工卡盘台和激光器的加工进给装置 光束施加装置，其中所述机器还包括用于检测所述卡盘台的加工进给量的进给量检测装置和用于基于来自所述进给量检测的检测信号来控制所述激光束施加装置的控制装置 并且所述控制装置基于来自所述进给量检测装置的信号，针对每个预定的处理进给量向所述激光束施加装置输出应用信号。

公开(公告)号：US07896194B2

公开(公告)日：2011-03-01

申请号：US11872512

申请日：2007-10-15

申请人： Kouji Sakota ,  Seiji Miura

发明人： Kouji Sakota ,  Seiji Miura

IPC分类号： A01C9/00

CPC分类号： B23P19/007 ,  B23K11/0053 ,  B23K11/36

摘要： A small-diameter front-end portion of a feed rod is allowed to enter into the screw hole of a nut delivered by a nut chute, and the nut is fed to an intended position by the forward movement of the feed rod. When an abnormal nut having a screw hole into which the small-diameter front-end portion cannot be inserted is delivered, the abnormal nut is prevented from being flicked by the feed rod. In order to achieve this, in a standby state, the small-diameter front-end portion of the feed rod enters a nut receiving chamber and is then stopped. On condition that the abnormal nut is received in the nut receiving chamber, if the feed rod moves forward to enter into the standby state, the abnormal nut is slightly pushed out forward from the nut receiving chamber.

摘要翻译： 进给杆的小直径前端部分被允许进入由螺母滑槽输送的螺母的螺孔中，并且通过进给杆的向前运动将螺母进给到预期位置。 当具有不能插入小直径前端部分的螺孔的异常螺母被输送时，防止异常螺母被进给杆弹起。 为了实现这一点，在待机状态下，进给棒的小直径前端部分进入螺母接收室，然后停止。 在螺母接收室中接收到异常螺母的情况下，如果进给杆向前移动进入待机状态，则异常螺母稍微从螺母接收室向前推出。

公开(公告)号：US07873796B2

公开(公告)日：2011-01-18

申请号：US11292218

申请日：2005-12-02

申请人： Seiji Miura

发明人： Seiji Miura

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F5/12 ,  G06F13/1663 ,  G06F13/1673

摘要： In an information processor system including a memory device (MEM0), a memory control device (SL0) capable of controlling an operation of the memory device, and a plurality of bus masters (MS0 to MS3) capable of giving access to the memory device through the memory control device, the memory control device includes a control circuit (SDCON) capable of giving a notice of information about a time that a data transfer from the memory device can be started to the bus master related to an access request. The bus master can cause the time information thus given to be a judgment factor as to whether an access request is given to the memory device or not. Consequently, each of the bus masters can avoid the generation of a useless access request and a data transfer to the masters to be accessed can be carried out smoothly.

摘要翻译： 在包括存储装置（MEM0），能够控制存储装置的动作的存储器控​​制装置（SL0）的信息处理器系统中，以及能够通过存储装置访问存储装置的多个总线主机（MS0〜MS3） 存储器控制装置，存储器控制装置包括控制电路（SDCON），该控制电路能够提供关于来自存储器装置的数据传输可以开始到与访问请求有关的总线主机的时间的信息的通知。 总线主机可以使得给出的时间信息成为关于是否向存储器件提供访问请求的判断因素。 因此，每个总线主机可以避免产生无用的访问请求，并且可以顺利地执行要访问的主机的数据传送。

公开(公告)号：US20090138597A1

公开(公告)日：2009-05-28

申请号：US12276010

申请日：2008-11-21

申请人： Roger Dwain Isaac ,  Seiji Miura

发明人： Roger Dwain Isaac ,  Seiji Miura

IPC分类号： G06F15/173 ,  G06F13/00

CPC分类号： G06F13/1673 ,  G06F13/1684

摘要： A storage system and method for storing information in memory nodes. The storage or memory nodes include a communication buffer. Flow of information to the storage nodes is controlled based upon constraints on the communication buffer. In one embodiment, communications between a master controller and a storage node have a determined maximum latency.

摘要翻译： 一种用于将信息存储在存储器节点中的存储系统和方法。 存储器或存储器节点包括通信缓冲器。 基于对通信缓冲器的约束来控制到存储节点的信息流。 在一个实施例中，主控制器和存储节点之间的通信具有确定的最大等待时间。