公开(公告)号：US08215505B2

公开(公告)日：2012-07-10

申请号：US10592028

申请日：2005-03-08

Applicant: Jeong-Min Lee ,  Seong-Jae Lee

Inventor： Jeong-Min Lee ,  Seong-Jae Lee

IPC: B65D47/00

CPC classification number: B65D51/2878 ,  B65D51/2864 ,  Y10S215/08

Abstract: A cap assembly that can be associated with a container storing a primary material includes a lid fixed on a top of the container and having an exhausting portion projected upward, a cap main body detachably coupled to the exhausting portion of the lid and having a storage tube extending downward to define a storage chamber for storing a secondary material, and an inner cap body detachably coupled to the storage tube.

Abstract translation: 可以与容纳主要材料的容器相关联的盖组件包括固定在容器的顶部上并具有向上突出的排出部分的盖，可拆卸地联接到盖的排出部分的盖主体，并具有储存管 向下延伸以限定用于存储次级材料的储存室，以及可拆卸地联接到储存管的内盖主体。

公开(公告)号：US20110197349A1

公开(公告)日：2011-08-18

申请号：US13029088

申请日：2011-02-16

Applicant: Seong-Jae LEE ,  Dennis O'Neel

Inventor： Seong-Jae LEE ,  Dennis O'Neel

IPC: A47K1/14

CPC classification number: F01M11/0408 ,  F01M2011/0416

Abstract: A drain plug comprising of a plurality of polarity magnets arranged in an alternating fashion. The plurality of polarity magnets are arranged in line with the drain plug. A magnet cover envelops the plurality of polarity magnets for easy cleaning. The unique alternating arrangements of the plurality of polarity magnets help increase the magnetic gradient for stronger attraction forces for metal wear particles. The use of a plurality of polarity magnets also increase the surface area where the metal particles can be held.

Abstract translation: 排水塞，其包括以交替方式布置的多个极性磁体。 多个极性磁体与排水塞一致排列。 磁体盖包围多个极性磁铁，以便于清洁。 多个极性磁体的独特交替布置有助于增加用于金属磨损颗粒的更强吸引力的磁梯度。 使用多个极性磁体也增加了可以保持金属颗粒的表面积。

公开(公告)号：US20090215232A1

公开(公告)日：2009-08-27

申请号：US12434779

申请日：2009-05-04

Applicant: Yark Yeon KIM ,  Seong Jae LEE ,  Moon Gyu JANG ,  Chel Jong CHOI ,  Myung Sim JUN ,  Byoung Chul PARK

Inventor： Yark Yeon KIM ,  Seong Jae LEE ,  Moon Gyu JANG ,  Chel Jong CHOI ,  Myung Sim JUN ,  Byoung Chul PARK

IPC: H01L21/338

CPC classification number: H01L29/47 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/7839

Abstract: Provided are a Schottky barrier tunnel transistor and a method of manufacturing the same that are capable of minimizing leakage current caused by damage to a gate sidewall of the Schottky barrier tunnel transistor using a Schottky tunnel barrier naturally formed at a semiconductor-metal junction as a tunnel barrier. The method includes the steps of: forming a semiconductor channel layer on an insulating substrate; forming a dummy gate on the semiconductor channel layer; forming a source and a drain at both sides of the dummy gate on the insulating substrate; removing the dummy gate; forming an insulating layer on a sidewall from which the dummy gate is removed; and forming an actual gate in a space from which the dummy gate is removed. In manufacturing the Schottky barrier tunnel transistor using the dummy gate, it is possible to form a high-k dielectric gate insulating layer and a metal gate, and stable characteristics in silicidation of the metal layer having very strong reactivity can be obtained.

Abstract translation: 提供了一种肖特基势垒隧道晶体管及其制造方法，该晶体管能够使用在半导体 - 金属结上自然形成的肖特基隧道势垒作为隧道来最小化对肖特基势垒隧道晶体管的栅极侧壁的损坏所造成的漏电流 屏障。 该方法包括以下步骤：在绝缘基板上形成半导体沟道层; 在半导体沟道层上形成虚拟栅极; 在绝缘基板上的虚拟栅极的两侧形成源极和漏极; 去除虚拟门; 在去除所述伪栅极的侧壁上形成绝缘层; 并且在从其中去除虚拟栅极的空间中形成实际栅极。 在使用伪栅极制造肖特基势垒隧道晶体管时，可以形成高k电介质栅极绝缘层和金属栅极，并且可以获得具有非常强反应性的金属层的硅化物的稳定特性。

公开(公告)号：US07545000B2

公开(公告)日：2009-06-09

申请号：US11485837

申请日：2006-07-13

Applicant: Yark Yeon Kim ,  Seong Jae Lee ,  Moon Gyu Jang ,  Chel Jong Choi ,  Myung Sim Jun ,  Byoung Chul Park

Inventor： Yark Yeon Kim ,  Seong Jae Lee ,  Moon Gyu Jang ,  Chel Jong Choi ,  Myung Sim Jun ,  Byoung Chul Park

IPC: H01L27/01

CPC classification number: H01L29/47 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/7839

Abstract: Provided are a Schottky barrier tunnel transistor and a method of manufacturing the same that are capable of minimizing leakage current caused by damage to a gate sidewall of the Schottky barrier tunnel transistor using a Schottky tunnel barrier naturally formed at a semiconductor-metal junction as a tunnel barrier. The method includes the steps of: forming a semiconductor channel layer on an insulating substrate; forming a dummy gate on the semiconductor channel layer; forming a source and a drain at both sides of the dummy gate on the insulating substrate; removing the dummy gate; forming an insulating layer on a sidewall from which the dummy gate is removed; and forming an actual gate in a space from which the dummy gate is removed. In manufacturing the Schottky barrier tunnel transistor using the dummy gate, it is possible to form a high-k dielectric gate insulating layer and a metal gate, and stable characteristics in silicidation of the metal layer having very strong reactivity can be obtained.

Abstract translation: 提供了一种肖特基势垒隧道晶体管及其制造方法，该晶体管能够使用在半导体 - 金属结上自然形成的肖特基隧道势垒作为隧道，将肖特基势垒隧道晶体管的栅极侧壁损坏所造成的漏电流减到最小 屏障。 该方法包括以下步骤：在绝缘基板上形成半导体沟道层; 在半导体沟道层上形成虚拟栅极; 在绝缘基板上的虚拟栅极的两侧形成源极和漏极; 去除虚拟门; 在去除所述伪栅极的侧壁上形成绝缘层; 并且在从其中去除虚拟栅极的空间中形成实际栅极。 在使用伪栅极制造肖特基势垒隧道晶体管时，可以形成高k电介质栅极绝缘层和金属栅极，并且可以获得具有非常强反应性的金属层的硅化物的稳定特性。

公开(公告)号：US20080254606A1

公开(公告)日：2008-10-16

申请号：US12090891

申请日：2006-12-04

Applicant: In Bok Baek ,  Seong Jae Lee ,  Jong Heon Yang ,  Chang Geun Ahn ,  Han Young Yu ,  Ki Ju Im

Inventor： In Bok Baek ,  Seong Jae Lee ,  Jong Heon Yang ,  Chang Geun Ahn ,  Han Young Yu ,  Ki Ju Im

IPC: H01L21/28

CPC classification number: H01L29/66439 ,  B82Y10/00 ,  H01L21/0273 ,  H01L21/28123 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66772 ,  H01L29/7613 ,  H01L29/7831

Abstract: Provided is a method of manufacturing a semiconductor device in which properties of photoresist through a lithography process are changed to form a dummy structure, and the structure is applied to a process of forming a gate electrode. The method includes the steps of: forming a buffer layer on the top of a semiconductor substrate; applying an inorganic photoresist on the buffer layer, and forming a photoresist pattern using a lithography process; thermally treating the photoresist pattern using a predetermined gas; uniformly depositing an insulating layer on the thermally treated structure, and etching the deposited layer by the deposited thickness in order to expose the thermally treated photoresist pattern; depositing an insulating layer on the etched structure, and etching the deposited insulating layer to expose the thermally treated photoresist pattern; removing the exposed photoresist pattern using an etching process; forming a gate oxide layer in the portion in which the photoresist pattern is removed; and forming a gate electrode on the gate oxide layer. Accordingly, in forming a structure for manufacturing a nano-sized device, the properties of the layer formed by a lithography process are improved through thermal treatment, and thus the structure used to manufacture various devices can be easily formed.

Abstract translation: 提供了通过光刻处理改变光致抗蚀剂的特性以形成虚拟结构的半导体器件的制造方法，并且将该结构应用于形成栅电极的工艺。 该方法包括以下步骤：在半导体衬底的顶部上形成缓冲层; 在缓冲层上施加无机光致抗蚀剂，并使用光刻工艺形成光致抗蚀剂图案; 使用预定气体热处理光刻胶图案; 在热处理结构上均匀沉积绝缘层，并通过沉积的厚度蚀刻沉积层，以暴露热处理的光致抗蚀剂图案; 在蚀刻的结构上沉积绝缘层，并蚀刻沉积的绝缘层以暴露热处理的光致抗蚀剂图案; 使用蚀刻工艺去除曝光的光致抗蚀剂图案; 在除去光致抗蚀剂图案的部分中形成栅氧化层; 以及在所述栅极氧化物层上形成栅电极。 因此，在形成纳米尺寸器件的制造结构时，通过热处理提高了通过光刻工艺形成的层的性质，因此可以容易地形成用于制造各种器件的结构。

公开(公告)号：US20080132049A1

公开(公告)日：2008-06-05

申请号：US11930902

申请日：2007-10-31

Applicant: Yark-Yeon KIM ,  Seong-Jae Lee ,  Moon-Gyu Jang ,  Tae-Youb Kim ,  Chel-Jong Choi ,  Myung-Sim Jun ,  Byoung-Chul Park

Inventor： Yark-Yeon KIM ,  Seong-Jae Lee ,  Moon-Gyu Jang ,  Tae-Youb Kim ,  Chel-Jong Choi ,  Myung-Sim Jun ,  Byoung-Chul Park

IPC: H01L21/334

CPC classification number: H01L29/78618 ,  H01L29/7839

Abstract: Provided is a method for fabricating a Schottky barrier tunnel transistor (SBTT) that can fundamentally prevent the generation of a gate leakage current caused by damage of spacers formed on both sidewalls of a gate electrode. The method for fabricating a Schottky barrier tunnel transistor, which includes: a) forming a silicon pattern and a sacrificial pattern on a buried oxide layer supported by a support substrate; b) forming a source/drain region on the buried oxide layer exposed on both sides of the silicon pattern, the source/drain region being formed of a metal layer and being in contact with both sidewalls of the silicon pattern; c) removing the sacrificial pattern to expose the top surface of the silicon pattern; and d) forming a gate insulating layer and a gate electrode on the exposed silicon pattern.

Abstract translation: 提供一种用于制造肖特基势垒隧道晶体管（SBTT）的方法，其可以从根本上防止由栅极电极的两个侧壁上形成的间隔物的损坏引起的栅极漏电流的产生。 一种制造肖特基势垒隧道晶体管的方法，包括：a）在由支撑衬底支撑的掩埋氧化物层上形成硅图案和牺牲图案; b）在暴露于硅图案的两侧的掩埋氧化物层上形成源极/漏极区域，源极/漏极区域由金属层形成并与硅图案的两个侧壁接触; c）去除牺牲图案以暴露硅图案的顶表面; 以及d）在暴露的硅图案上形成栅极绝缘层和栅电极。

公开(公告)号：US20080125033A1

公开(公告)日：2008-05-29

申请号：US11944695

申请日：2007-11-26

Applicant: Seong Jae Lee ,  Mi Ja Lee ,  Chang Soon Kim ,  Hyeong Soo Choi

Inventor： Seong Jae Lee ,  Mi Ja Lee ,  Chang Soon Kim ,  Hyeong Soo Choi

IPC: H04B7/14

CPC classification number: H04B7/15585

Abstract: The present invention relates to a Radio Frequency Repeater to prevent oscillation with canceling a feedback interference signal between transmitting and receiving antenna with built-in transmitting and receiving antenna in wireless mobile communication repeater.A radio frequency repeater for canceling a feedback interference signal has a downlink path from a base station to a terminal and an uplink path from a terminal to a base station, and said downlink path and said uplink path is separated and combination by a duplexer.

Abstract translation: 本发明涉及一种无线电频率中继器，用于在无线移动通信中继器中利用内置发射和接收天线消除发射和接收天线之间的反馈干扰信号来防止振荡。 用于消除反馈干扰信号的射频中继器具有从基站到终端的下行链路路径和从终端到基站的上行链路路径，并且所述下行链路路径和所述上行链路路径被双工器分离并组合。

公开(公告)号：US20080121868A1

公开(公告)日：2008-05-29

申请号：US11800914

申请日：2007-05-08

Applicant: Moon-Gyu Jang ,  Yark-Yeon Kim ,  Chel-Jong Choi ,  Myung-Sim Jun ,  Tae-Youb Kim ,  Seong-Jae Lee

Inventor： Moon-Gyu Jang ,  Yark-Yeon Kim ,  Chel-Jong Choi ,  Myung-Sim Jun ,  Tae-Youb Kim ,  Seong-Jae Lee

IPC: H01L29/47 ,  H01L21/338

CPC classification number: H01L29/8126 ,  H01L29/66409

Abstract: A Schottky barrier tunnel transistor includes a gate electrode, and source and drain regions. The gate electrode is formed over a channel region of a substrate to form a Schottky junction with the substrate. The source and drain regions are formed in the substrate exposed on both sides of the gate electrode.

Abstract translation: 肖特基势垒隧道晶体管包括栅极电极和源极和漏极区域。 栅电极形成在衬底的沟道区上，以与衬底形成肖特基结。 源极和漏极区域形成在暴露于栅电极两侧的衬底中。

公开(公告)号：US07195962B2

公开(公告)日：2007-03-27

申请号：US10833452

申请日：2004-04-27

Applicant: Wonju Cho ,  Seong Jae Lee ,  Jong Heon Yang ,  Jihun Oh ,  Kiju Im ,  Chang Geun Anh

Inventor： Wonju Cho ,  Seong Jae Lee ,  Jong Heon Yang ,  Jihun Oh ,  Kiju Im ,  Chang Geun Anh

IPC: H01L21/00

CPC classification number: H01L29/78696 ,  H01L21/28114 ,  H01L21/30608 ,  H01L29/045 ,  H01L29/1033 ,  H01L29/42376 ,  H01L29/4908 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66772

Abstract: Provided is a MOSFET with an ultra short channel length and a method of fabricating the same. The ultra short channel MOSFET has a silicon wire channel region with a three-dimensional structure, and a source/drain junction formed in a silicon conductive layer formed of both sides of the silicon wire channel region. Also, a gate electrode formed on the upper surface of the silicon wire channel region by interposing a gate insulating layer having a high dielectric constant therebetween, and source and drain electrodes connected to the source/drain junction are included. The silicon wire channel region is formed with a triangular or trapezoidal section by taking advantage of different etch rates that depend on the planar orientation of the silicon. The source/drain junction is formed by a solid-state diffusion method.

Abstract translation: 提供了具有超短沟道长度的MOSFET及其制造方法。 超短沟道MOSFET具有三维结构的硅线沟道区，以及形成在由硅线沟道区的两侧形成的硅导电层中的源极/漏极结。 此外，包括在其间具有高介电常数的栅极绝缘层，以及连接到源极/漏极结的源极和漏极，形成在硅线沟道区的上表面上的栅电极。 通过利用取决于硅的平面取向的不同蚀刻速率，硅线沟道区域形成有三角形或梯形截面。 源极/漏极结通过固态扩散方法形成。

公开(公告)号：US06999772B2

公开(公告)日：2006-02-14

申请号：US10452633

申请日：2003-06-03

Applicant: Bong Yong Song ,  Jeong Chul Kim ,  Youl No Lee ,  Gab Seok Jang ,  Se Hyun Oh ,  Seong Jae Lee

Inventor： Bong Yong Song ,  Jeong Chul Kim ,  Youl No Lee ,  Gab Seok Jang ,  Se Hyun Oh ,  Seong Jae Lee

IPC: H04Q7/20

CPC classification number: H04W72/0466 ,  H04B17/318 ,  H04B17/382 ,  H04B2201/70702 ,  H04W16/14 ,  H04W28/26 ,  H04W52/0206 ,  H04W72/02 ,  H04W72/0453 ,  H04W72/082 ,  H04W76/10 ,  H04W84/042 ,  Y02D70/00

Abstract: A method for assigning a channel in multi-FA CDMA mobile communication system according to the received power prevents communication quality of a FA from being inferior to that of the others by managing the interference level of the FA. The method comprises the steps of: comparing a first threshold value with received power when the base station receives a new call request; assigning a traffic channel in a first FA of the request, if the received power is less than the first threshold value, and searching a second FA of which received power is least, if not; comparing a second threshold value with the received power of the second FA; and assigning a traffic channel in the second FA if the received power is less than the second threshold value, and rejecting the request, if not.