公开(公告)号：US10056355B2

公开(公告)日：2018-08-21

申请号：US15803248

申请日：2017-11-03

申请人： TAIWAN SEMICONDUCTOR CO., LTD.

发明人： Chien-Chung Chen ,  Sen Mao ,  Hsin-Liang Lin

IPC分类号： H01L23/495 ,  H01L25/07 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L25/072 ,  H01L23/3121 ,  H01L24/06 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/371 ,  H01L2224/40101 ,  H01L2224/40137 ,  H01L2224/40245 ,  H01L2224/48101 ,  H01L2224/48137 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2224/84 ,  H01L2224/45099

摘要： A common-source type package structure is provided in the present invention. In the package structure, an integrated component body is configured a common-source pin region, a first arrangement region and a second arrangement region. The second and first arrangement regions are spaced apart from each other. A first MOSFET die and a second MOSFET are respectively located at the first and second arrangement region respectively, and have a top surface, a source electrode pad and a gate electrode pad. The source electrode pad and the gate electrode pad are exposed to the top surface and spaced apart from each other. A common-source connection element is connected to the source electrode pad and the common-source pin region. A gate connection element is connected to the gate electrode pad and a gate pin region of the integrated component body.

公开(公告)号：US20180090580A1

公开(公告)日：2018-03-29

申请号：US15686564

申请日：2017-08-25

申请人： TAIWAN SEMICONDUCTOR CO., LTD.

发明人： Yi-Lung TSAI ,  Aryadeep MRINAL ,  Mohammad AMANULLAH ,  Po-Wen YANG ,  Shu-Siang LIANG

IPC分类号： H01L29/423 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L29/4236 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/513 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： A field effect transistor includes a substrate, an epitaxial layer, a remnant-oxide layer, an electrode, a surrounding-oxide layer, a surrounding-nitride layer, a gate oxide layer, a gate, a P-body region, a source region, an interlayer dielectric and a source electrode. The epitaxial layer on the substrate has a trench having a sidewall and a bottom. The electrode inside the trench is coated subsequently by the surrounding-oxide layer, the surrounding-nitride layer and the remnant-oxide layer. The gate formed on the gate oxide layer is separated from the electrode sequentially by the gate oxide layer, the surrounding-nitride layer and the surrounding-oxide layer. The P-body region and the source region, formed at the epitaxial layer, are separated from the gate by the gate oxide layer. The interlayer dielectric covers the source region and the gate. The source electrode covers the P-body region and the interlayer dielectric, and contacts the source region.

公开(公告)号：US20180053849A1

公开(公告)日：2018-02-22

申请号：US15270498

申请日：2016-09-20

申请人： TAIWAN SEMICONDUCTOR CO., LTD.

发明人： Yi-Lung TSAI ,  Aryadeep MRINAL ,  Mohammad AMANULLAH ,  Po-Wen YANG ,  Shu-Siang LIANG

IPC分类号： H01L29/78 ,  H01L21/306 ,  H01L21/311 ,  H01L21/285 ,  H01L29/40 ,  H01L29/49 ,  H01L29/423

CPC分类号： H01L29/7831 ,  H01L21/28525 ,  H01L21/30604 ,  H01L21/31111 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4916

摘要： A field effect transistor is manufactured by firstly forming an epitaxial layer on a substrate. Then, a trench having an oxide layer is formed on the epitaxial layer. The oxide layer has a first electrode portion having a first width and a first height and a second electrode portion having a second width and a second height. A gate oxide layer covering the oxide layer and the second electrode portion has a gate portion having a third width. The epitaxial layer has a body region and a source region, where these two regions are adjacent to the gate portion and covered by an interlayer dielectric. A source electrode covering the body region and the interlayer dielectric contacts the source region. The first height is no less than the second height, the first width is smaller than the second width, and the second width is smaller than the third width.

公开(公告)号：US09799742B1

公开(公告)日：2017-10-24

申请号：US15356927

申请日：2016-11-21

申请人： TAIWAN SEMICONDUCTOR CO., LTD.

发明人： Yi-Lung Tsai ,  Aryadeep Mrinal ,  Mohammad Amanullah ,  Po-Wen Yang ,  Shu-Siang Liang

IPC分类号： H01L29/788 ,  H01L29/423 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/4236 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/513 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： A field effect transistor includes a substrate, an epitaxial layer, a remnant-oxide layer, an electrode, a surrounding-oxide layer, a surrounding-nitride layer, a gate oxide layer, a gate, a P-body region, a source region, an interlayer dielectric and a source electrode. The epitaxial layer on the substrate has a trench having a sidewall and a bottom. The electrode inside the trench is coated subsequently by the surrounding-oxide layer, the surrounding-nitride layer and the remnant-oxide layer. The gate formed on the gate oxide layer is separated from the electrode sequentially by the gate oxide layer, the surrounding-nitride layer and the surrounding-oxide layer. The P-body region and the source region, formed at the epitaxial layer, are separated from the gate by the gate oxide layer. The interlayer dielectric covers the source region and the gate. The source electrode covers the P-body region and the interlayer dielectric, and contacts the source region.

公开(公告)号：US08779545B2

公开(公告)日：2014-07-15

申请号：US13737233

申请日：2013-01-09

申请人： Taiwan Semiconductor Co., Ltd.

发明人： Chao-Hsin Huang ,  Chih-Chiang Chuang

IPC分类号： H01L29/06

CPC分类号： H01L29/0692 ,  H01L21/26586 ,  H01L29/47 ,  H01L29/8725

摘要： A semiconductor structure with dispersedly arranged active region trenches is provided. The semiconductor structure comprises a semiconductor substrate, an epitaxial layer, and an active region dielectric layer. The semiconductor substrate is doped with impurities of a first conductive type having a first impurity concentration. The epitaxial layer is doped with impurities of the first conductive type having a second impurity concentration and is formed on the semiconductor substrate. The epitaxial layer has a plurality of active region trenches formed therein being arranged in a dispersed manner. The active region dielectric layer covers a bottom and a sidewall of the active region trenches. Wherein, the active region trench has an opening in a tetragonal shape on a surface of the epitaxial layer, and the first impurity concentration is greater than the second impurity concentration.

摘要翻译： 提供了具有分散布置的有源区沟槽的半导体结构。 半导体结构包括半导体衬底，外延层和有源区介电层。 半导体衬底掺杂有具有第一杂质浓度的第一导电类型的杂质。 外延层掺杂有具有第二杂质浓度的第一导电类型的杂质并形成在半导体衬底上。 外延层具有形成在其中的多个有源区沟槽以分散的方式布置。 有源区介电层覆盖有源区沟槽的底部和侧壁。 其中，有源区沟槽在外延层的表面上具有四边形形状的开口，并且第一杂质浓度大于第二杂质浓度。

公开(公告)号：US11640994B2

公开(公告)日：2023-05-02

申请号：US17572648

申请日：2022-01-11

申请人： IPOWER SEMICONDUCTOR ,  Taiwan Semiconductor Co., Ltd.

发明人： Hamza Yilmaz ,  Jong Oh Kim

IPC分类号： H01L29/423 ,  H01L29/78 ,  H01L29/66

摘要： A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.

公开(公告)号：US11177342B1

公开(公告)日：2021-11-16

申请号：US16935991

申请日：2020-07-22

申请人： TAIWAN SEMICONDUCTOR CO., LTD.

发明人： Yi-Lung Tsai ,  Syed Sarwar Imam ,  Yao-Wei Chuang ,  Ming-Lou Tung

IPC分类号： H01L29/06 ,  H01L29/872 ,  H01L29/66

摘要： A Schottky diode with multiple guard ring structures includes a semiconductor base layer, a back metal layer, an epitaxial layer, a dielectric layer, a first metal layer, a passivation layer and a second metal layer. The epitaxial layer on the semiconductor base layer includes a terminal trench structure, a first ion implantation guard ring, a second ion implantation guard ring and a third ion implantation guard ring. The dielectric layer is on the epitaxial layer in a termination area. The first metal layer is on the terminal trench structure and the dielectric layer. The passivation layer is on the first metal layer and the dielectric layer. The second metal layer is on the first metal layer and the passivation layer. Widths of the first, second and third ion implantation guard rings decrease in order, so that the voltage can be distributed step by step.

公开(公告)号：US20180211953A1

公开(公告)日：2018-07-26

申请号：US15447800

申请日：2017-03-02

申请人： TAIWAN SEMICONDUCTOR CO., LTD.

发明人： Chien-Chung CHEN ,  Sen MAO ,  Hsin-Liang LIN

IPC分类号： H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L23/495

CPC分类号： H01L27/088 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49586 ,  H01L29/0634 ,  H01L29/41725

摘要： An integrated packaging structure is provided. In the package structure, an integrated component body has a first source region, a second source region, a first setting region, and a second setting region, which are separated from each other. A first MOSFET die and a second MOSFET die are located on the first setting region and the second setting region respectively, and have a top surface, a source electrode pad and a gate electrode pad. The source electrode pad and the gate electrode pad are exposed from the top surface and spaced apart from each other. A first source connection element is connected to the source electrode pad of the first MOSFET die and the first source region. A second source connection element is connected to the source electrode pad of the second MOSFET die and the second source region. A gate connection element is connected to the gate electrode pad and a gate region of the integrated component body.

公开(公告)号：US09960244B2

公开(公告)日：2018-05-01

申请号：US15686564

申请日：2017-08-25

申请人： TAIWAN SEMICONDUCTOR CO., LTD.

发明人： Yi-Lung Tsai ,  Aryadeep Mrinal ,  Mohammad Amanullah ,  Po-Wen Yang ,  Shu-Siang Liang

IPC分类号： H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/4236 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/513 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： A field effect transistor includes a substrate, an epitaxial layer, a remnant-oxide layer, an electrode, a surrounding-oxide layer, a surrounding-nitride layer, a gate oxide layer, a gate, a P-body region, a source region, an interlayer dielectric and a source electrode. The epitaxial layer on the substrate has a trench having a sidewall and a bottom. The electrode inside the trench is coated subsequently by the surrounding-oxide layer, the surrounding-nitride layer and the remnant-oxide layer. The gate formed on the gate oxide layer is separated from the electrode sequentially by the gate oxide layer, the surrounding-nitride layer and the surrounding-oxide layer. The P-body region and the source region, formed at the epitaxial layer, are separated from the gate by the gate oxide layer. The interlayer dielectric covers the source region and the gate. The source electrode covers the P-body region and the interlayer dielectric, and contacts the source region.