公开(公告)号：US20140231868A1

公开(公告)日：2014-08-21

申请号：US14166215

申请日：2014-01-28

申请人： Tatsuji NAGAOKA

发明人： Tatsuji NAGAOKA

IPC分类号： H01L29/423 ,  H01L29/739

CPC分类号： H01L29/7393 ,  H01L23/4824 ,  H01L29/7397 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate and a first electrode. An element region, and a non-element region that surrounds this element region, are formed on the semiconductor substrate. The first electrode is arranged on the semiconductor substrate and is electrically connected to the element region formed on the semiconductor substrate. The first electrode is made of at least two materials having different moduli of elasticity. A modulus of elasticity per unit area of an outer peripheral portion of the first electrode when the semiconductor substrate is viewed from above is smaller than a modulus of elasticity per unit area of a center portion of the first electrode.

摘要翻译： 半导体器件包括半导体衬底和第一电极。 元件区域和围绕该元件区域的非元件区域形成在半导体衬底上。 第一电极布置在半导体衬底上，并且电连接到形成在半导体衬底上的元件区域。 第一电极由具有不同弹性模量的至少两种材料制成。 当从上方观察半导体衬底时，第一电极的外围部分的每单位面积的弹性模量小于第一电极的中心部分的每单位面积的弹性模量。

公开(公告)号：US20120007142A1

公开(公告)日：2012-01-12

申请号：US13242960

申请日：2011-09-23

申请人： Tatsuji NAGAOKA ,  Akitaka SOENO

发明人： Tatsuji NAGAOKA ,  Akitaka SOENO

IPC分类号： H01L27/06

CPC分类号： H01L21/761 ,  H01L27/0727 ,  H01L29/32 ,  H01L29/7397 ,  H01L29/861

摘要： Provided is a semiconductor device including a semiconductor substrate in which a diode region and an IGBT region are formed. A separation region formed of a p-type semiconductor is formed in a range between the diode region and the IGBT region and extending from an upper surface of the semiconductor substrate to a position deeper than both a lower end of an anode region and a lower end of a body region. A diode lifetime control region is formed within a diode drift region. A carrier lifetime in the diode lifetime control region is shorter than that in the diode drift region outside the diode lifetime control region. An end of the diode lifetime control region on an IGBT region side is located right below the separation region.

摘要翻译： 提供一种半导体器件，其包括其中形成二极管区域和IGBT区域的半导体衬底。 在二极管区域和IGBT区域之间的范围内形成由p型半导体形成的分离区域，并且从半导体衬底的上表面延伸到比阳极区域和下端部的下端更深的位置 的身体区域。 二极管寿命控制区形成在二极管漂移区内。 二极管寿命控制区域中的载流子寿命短于二极管寿命控制区域外的二极管漂移区域中的载流子寿命。 IGBT区域侧的二极管寿命控制区域的一端位于分离区域正下方。

公开(公告)号：US07898024B2

公开(公告)日：2011-03-01

申请号：US12023637

申请日：2008-01-31

申请人： Akio Sugi ,  Tatsuji Nagaoka ,  Hong-fei Lu

发明人： Akio Sugi ,  Tatsuji Nagaoka ,  Hong-fei Lu

IPC分类号： H01L29/76 ,  H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0653 ,  H01L29/408 ,  H01L29/42368 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66734

摘要： In a MIS-type semiconductor device having a trench gate structure, a withstand voltage is ensured without changing the thickness of a drift layer and on-resistance can be reduced without applying a high gate drive voltage. The lower half of a trench extending through a p-base region into an n-drift region is filled with a high-permittivity dielectric having a relative permittivity that is higher than that of a silicon oxide film, preferably a silicon nitride film, and an insulated gate structure including a gate insulator and a gate electrode is fabricated on the high-permittivity dielectric. The depth d2 of the deepest portion of the high-permittivity dielectric is designed to be deeper than the depth d1 of a depletion layer in the semiconductor region away from the high-permittivity dielectric.

摘要翻译： 在具有沟槽栅极结构的MIS型半导体器件中，在不改变漂移层的厚度的情况下确保耐受电压，并且可以在不施加高栅极驱动电压的情况下降低导通电阻。 将通过p基区域延伸到n漂移区域的沟槽的下半部分填充有具有比氧化硅膜，优选氮化硅膜更高的相对介电常数的高介电常数电介质，以及 包括栅极绝缘体和栅电极的绝缘栅极结构被制造在高介电常数电介质上。 高介电常数电介质的最深部分的深度d2被设计为比离开高介电常数电介质的半导体区域中的耗尽层的深度d1更深。

公开(公告)号：US06768167B2

公开(公告)日：2004-07-27

申请号：US10442647

申请日：2003-05-21

申请人： Tatsuji Nagaoka ,  Tatsuhiko Fujihira ,  Yasuhiko Onishi

发明人： Tatsuji Nagaoka ,  Tatsuhiko Fujihira ,  Yasuhiko Onishi

IPC分类号： H01L2976

CPC分类号： H01L29/7802 ,  H01L27/0207 ,  H01L29/0696 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： A MIS semiconductor device has a greatly improved relation between the on-resistance and the switching time by forming trench completely through a p base region and positioning the trench adjacent to a gate electrode, and then implanting n-type impurity ions using the gate electrode as a mask to form a second drain region, which also serves as a drift region.

公开(公告)号：US06724042B2

公开(公告)日：2004-04-20

申请号：US09781066

申请日：2001-02-09

申请人： Yasuhiko Onishi ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Susumu Iwamoto ,  Takahiro Sato ,  Tatsuji Nagaoka

发明人： Yasuhiko Onishi ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Susumu Iwamoto ,  Takahiro Sato ,  Tatsuji Nagaoka

IPC分类号： H01L2976

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a semiconductor device facilitating a peripheral portion thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate. A preferred embodiment includes a drain drift region with a first alternating conductivity type layer formed of n drift current path regions and p partition regions arranged alternately with each other, and a breakdown withstanding region with a second alternating conductivity type layer formed of n regions and p regions arranged alternately with each other, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device. Since depletion layers expand in both directions from multiple pn-junctions into n regions and p regions in the OFF-state of the device, the adjacent areas of p-type base regions, the outer area of the semiconductor chip and the deep area of the semiconductor chip are depleted. Thus, the breakdown voltage of breakdown withstanding region is higher than the breakdown voltage of drain drift region.

摘要翻译： 公开了一种半导体器件，其使用其周边部分具有高于漏极漂移层中的击穿电压的击穿电压，而不采用保护环或场板。 优选实施例包括漏极漂移区，其具有由n个漂移电流通路区域和彼此交替布置的p个分隔区域形成的第一交变导电类型层，以及具有由n个区域和p形成的第二交变导电类型层的击穿承受区域 区域彼此交替布置，击穿承受区域在设备的接通状态下不提供电流路径，并且在器件的关断状态被耗尽。 由于耗尽层从多个pn结到两个方向扩展到设备的OFF状态的n个区域和p区域，所以p型基极区域的相邻区域，半导体芯片的外部区域和 半导体芯片耗尽。 因此，击穿耐受区域的击穿电压高于漏极漂移区域的击穿电压。

公开(公告)号：US11534791B2

公开(公告)日：2022-12-27

申请号：US15931968

申请日：2020-05-14

申请人： Tatsuji Nagaoka ,  Hiroyuki Nishinaka ,  Masahiro Yoshimoto

发明人： Tatsuji Nagaoka ,  Hiroyuki Nishinaka ,  Masahiro Yoshimoto

IPC分类号： B05B17/06 ,  B05B7/00 ,  H01L21/02

摘要： A mist generator may include a reservoir storing a solution, a plurality of ultrasonic vibrators, a mist delivery path, and a mist collector. The plurality of ultrasonic vibrators may be disposed under the reservoir and configured to apply ultrasonic vibration to the solution stored in the reservoir to generate mist of the solution in the reservoir. The mist delivery path may be configured to deliver the mist from an inside of the reservoir to an outside of the reservoir. The mist collector may be disposed above the solution in the reservoir, wherein an upper end of the mist collector may be connected to an upstream end of the mist delivery path, a lower end of the mist collector may include an opening, and a width of the mist collector may increase from the upper end toward the opening. The plurality of ultrasonic vibrators may be located directly under the opening.

公开(公告)号：US11443944B2

公开(公告)日：2022-09-13

申请号：US16859160

申请日：2020-04-27

申请人： Tatsuji Nagaoka ,  Hiroyuki Nishinaka ,  Masahiro Yoshimoto ,  Daisuke Tahara

发明人： Tatsuji Nagaoka ,  Hiroyuki Nishinaka ,  Masahiro Yoshimoto ,  Daisuke Tahara

IPC分类号： H01L21/16 ,  H01L21/02

摘要： A method of growing semiconductor layers may include: growing a first semiconductor layer on a surface of a substrate at which a crystal layer is exposed, wherein the first semiconductor layer is different from the crystal layer in at least one of a material and a crystal structure; cutting the first semiconductor layer such that a cut surface of the first semiconductor layer extends from a front surface of the first semiconductor layer to a rear surface of the first semiconductor layer; and growing a second semiconductor layer on the cut surface of the first semiconductor layer, wherein the second semiconductor layer has a material and a crystal structure that are same as those of the first semiconductor layer.

公开(公告)号：US20200243333A1

公开(公告)日：2020-07-30

申请号：US16741060

申请日：2020-01-13

申请人： Tatsuji NAGAOKA ,  Hiroyuki NISHINAKA ,  Daisuke TAHARA ,  Masahiro YOSHIMOTO

发明人： Tatsuji NAGAOKA ,  Hiroyuki NISHINAKA ,  Daisuke TAHARA ,  Masahiro YOSHIMOTO

IPC分类号： H01L21/02 ,  B05B17/06

摘要： A film formation apparatus is configured to supply mist of a solution to a surface of a substrate so as to epitaxially grow a film on the surface of the substrate. The film formation apparatus may be provided with: a furnace configured to house and heat the substrate; a reservoir configured to store the solution; a heater configured to heat the solution in the reservoir; an ultrasonic transducer configured to apply ultrasound to the solution in the reservoir so as to generate the mist of the solution in the reservoir; and a mist supply path configured to carry the mist from the reservoir to the furnace.

公开(公告)号：US20200027730A1

公开(公告)日：2020-01-23

申请号：US16512442

申请日：2019-07-16

申请人： Tatsuji NAGAOKA ,  Hiroyuki NISHINAKA ,  Masahiro YOSHIMOTO

发明人： Tatsuji NAGAOKA ,  Hiroyuki NISHINAKA ,  Masahiro YOSHIMOTO

IPC分类号： H01L21/02 ,  C30B29/26 ,  H01L21/288

摘要： A film forming method of forming an oxide film on a substrate, wherein the oxide film has germanium doped therein and comprises a property of a conductor or a semiconductor, is disclosed herein. The film forming method may include supplying mist of a solution to a surface of the substrate while heating the substrate, wherein an oxide film material including a constituent element of the oxide film and an organic germanium compound may be dissolved in the solution.

公开(公告)号：US09147759B1

公开(公告)日：2015-09-29

申请号：US14614991

申请日：2015-02-05

申请人： Tatsuji Nagaoka

发明人： Tatsuji Nagaoka

IPC分类号： H01L29/00 ,  H01L29/739 ,  H01L29/417 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/7815 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7397 ,  H01L2924/13055

摘要： A semiconductor device disclosed herein is configured such that a well region including a well layer is disposed between a main region of a semiconductor substrate and a current sense region of the semiconductor substrate, that a well region electrode is disposed above the well region, and that the well layer and the well region electrode are in contact with each other through a contact hole formed in an interlayer insulating film.

摘要翻译： 本文公开的半导体器件被配置为使得包括阱层的阱区被布置在半导体衬底的主区域和半导体衬底的电流感测区域之间，阱区电极设置在阱区上方，并且 阱层和阱区电极通过形成在层间绝缘膜中的接触孔彼此接触。