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    METHOD AND APPARATUS FOR STACKING MULTI-TEMPORAL MAI INTERFEROGRAMS
    33.
    发明申请
    METHOD AND APPARATUS FOR STACKING MULTI-TEMPORAL MAI INTERFEROGRAMS 有权
    用于堆叠多时间间隔的方法和装置

    公开(公告)号：US20160033639A1

    公开(公告)日：2016-02-04

    申请号：US14817699

    申请日：2015-08-04

    Applicant: University of Seoul Industry Cooperation Foundation

    Inventor： Hyung Sup Jung ,  Min-Jeong Jo

    IPC: G01S13/90

    CPC classification number: G01S13/9023

    Abstract: An apparatus and method for stacking multi-temporal MAI interferograms Disclosed are disclosed herein. The apparatus includes a processor configured to: generate a forward-looking InSAR (Interferometric Synthetic Aperture Radar) interferogram and a backward-looking InSAR interferogram of multi-temporal interferometric pairs; generate a residual forward-looking interferogram and a residual backward-looking interferogram by removing low-frequency phase components from the forward-looking InSAR interferogram and the backward-looking InSAR interferogram; generate a stacked forward-looking interferogram and a stacked backward-looking interferogram by separately stacking the residual forward-looking interferogram and the residual backward-looking interferogram; and generate a stacked MAI interferogram based on a phase difference between the stacked forward-looking interferogram and the stacked backward-looking interferogram.

    Abstract translation: 用于叠加多时间MAI干涉图的装置和方法公开了本文。 该装置包括：处理器，被配置为：产生前瞻性InSAR（干涉合成孔径雷达）干涉图和多时间干涉测量对的后视InSAR干涉图; 通过从前瞻性InSAR干涉图和后向InSAR干涉图去除低频相位分量，产生残留的前视干涉图和残留的后视干涉图; 通过分别堆积残留的前视干涉图和剩余后视干涉图来产生堆积的前视干涉图和堆叠的后向干涉图; 并且基于堆叠的前视干涉图和堆叠的后向干涉图之间的相位差产生堆叠的MAI干涉图。

    Power factor correction circuit
    34.
    发明授权
    Power factor correction circuit 有权
    功率因数校正电路

    公开(公告)号：US09225235B2

    公开(公告)日：2015-12-29

    申请号：US13892013

    申请日：2013-05-10

    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD. ,  University of Seoul Industry Cooperation Foundation

    Inventor： Yu Jin Jang ,  Hwan Cho ,  Yong Seong Roh ,  Young Jin Moon ,  Jeong Pyo Park ,  Chang Sik Yoo ,  Jeong Mo Yang ,  Joong Ho Choi

    IPC: H02M1/36 ,  H02M1/42 ,  H02M1/00

    CPC classification number: H02M1/36 ,  H02M1/4225 ,  H02M2001/0022 ,  Y02B70/126

    Abstract: There is provided a power factor correction circuit including: a power conversion circuit unit controlling an inductor current according to a switching signal applied to a main switch to convert an external input voltage into an output voltage having a predetermined range; an imbalance detection circuit outputting an imbalance state signal when the external input voltage is in an unbalanced state by using the inductor current; and a soft start circuit unit performing soft starting by adjusting the switching signal when the imbalance state signal is output by the imbalance detection circuit unit.

    Abstract translation: 提供了一种功率因数校正电路，包括：功率转换电路单元，根据施加到主开关的开关信号来控制电感器电流，以将外部输入电压转换成具有预定范围的输出电压; 当外部输入电压通过使用电感器电流处于不平衡状态时，输出不平衡状态信号的不平衡检测电路; 以及软启动电路单元，通过在由不平衡检测电路单元输出不平衡状态信号时调节开关信号来进行软启动。

    SYSTEM AND METHOD FOR CALCULATING ARRANGEMENT DATA BETWEEN DEVICES
    35.
    发明申请
    SYSTEM AND METHOD FOR CALCULATING ARRANGEMENT DATA BETWEEN DEVICES 有权
    用于计算设备之间的安排数据的系统和方法

    公开(公告)号：US20150256606A1

    公开(公告)日：2015-09-10

    申请号：US14637745

    申请日：2015-03-04

    Applicant: UNIVERSITY OF SEOUL INDUSTRY COOPERATION FOUNDATION

    Inventor： Jin Suk KIM

    IPC: H04L29/08 ,  G06F3/0484 ,  H04W4/00

    CPC classification number: H04L67/10 ,  H04M1/67 ,  H04M1/7253 ,  H04W4/70 ,  H04W4/80

    Abstract: A method for calculating arrangement data between devices includes: receiving an input of a first point on a display of a first device; receiving an input of a second point on a display of a second device; and calculating arrangement data between the first device and the second device based on data of a virtual straight line connecting the first point and the second point, and the arrangement data include a distance between the first device and the second device and an angle between the first device and the second device.

    Abstract translation: 一种用于计算装置之间的布置数据的方法包括：接收第一装置的显示器上的第一点的输入; 在第二设备的显示器上接收第二点的输入; 以及基于连接所述第一点和所述第二点的虚拟直线的数据来计算所述第一设备和所述第二设备之间的排列数据，并且所述排列数据包括所述第一设备和所述第二设备之间的距离，以及所述第一设备和所述第二设备之间的角度 设备和第二设备。

    Method and System for Determining the Location and Position of a Smartphone Based on Image Matching
    36.
    发明申请
    Method and System for Determining the Location and Position of a Smartphone Based on Image Matching 有权
    基于图像匹配确定智能手机的位置和位置的方法和系统

    公开(公告)号：US20150126223A1

    公开(公告)日：2015-05-07

    申请号：US14397275

    申请日：2012-11-14

    Applicant: University of Seoul Industry Cooperation Foundation

    Inventor： Im Pyeong Lee ,  Kyoung Ah Choi ,  Ho Jun Kim

    IPC: H04W4/04 ,  H04W4/02

    CPC classification number: H04W4/04 ,  G01S5/0009 ,  G06T7/74 ,  G06T2207/30244 ,  H04L67/18 ,  H04W4/021 ,  H04W4/027

    Abstract: The present invention relates to a method and system for determining location and position for the effective use thereof in a location-based service by precisely determining information on the location and position of a user terminal, such as a smartphone, to provide the determined location and position to the user terminal using a georeferenced reference image DB preconstructed on a server on a network or on the user terminal, and images captured by a camera of the user terminal.

    Abstract translation: 本发明涉及一种用于通过精确地确定诸如智能电话之类的用户终端的位置和位置的信息来确定在基于位置的服务中有效使用位置和位置的方法和系统，以提供确定的位置和 使用在网络或用户终端上的服务器上预先构建的地理参考的参考图像DB的用户终端的位置以及由用户终端的照相机拍摄的图像。

    IC circuit
    37.
    发明授权
    IC circuit 有权
    IC电路

    公开(公告)号：US08907719B2

    公开(公告)日：2014-12-09

    申请号：US13678491

    申请日：2012-11-15

    Applicant: Samsung Electro-Mechanics Co., Ltd. ,  University of Seoul Industry Cooperation Foundation

    Inventor： Joon Youp Sung ,  Jae Shin Lee ,  Joong Ho Choi ,  Yong Seong Roh ,  Ho Joon Jang ,  Chang Sik Yoo ,  Jung Sun Kwon ,  Young Jin Moon

    IPC: G05F1/10 ,  G05F3/16

    CPC classification number: G05F3/16 ,  G05F3/26

    Abstract: The present invention relates to an IC circuit. In an embodiment, an IC circuit includes: an RT terminal connected to an external; a current mirroring unit conducting a channel current between internal voltage power and the RT terminal and generating an internal reference current mirrored with the channel current; a negative feedback unit receiving the internal reference current, equalizing voltages of an RT terminal connection terminal and an internal reference current output terminal of the current mirroring unit to make the internal reference current constant, and providing the internal reference current inside the IC circuit; and an IC state indicating unit having a transistor, which operates complementarily with the current mirroring unit, connected between the RT terminal and a ground and providing the state of an IC or a system to the RT terminal by being linked with the complementary operation of the current mirroring unit.

    Abstract translation: IC电路技术领域本发明涉及IC电路。 在一个实施例中，IC电路包括：连接到外部的RT终端; 电流镜像单元，在内部电压电源和RT端子之间进行通道电流，并产生与通道电流镜像的内部参考电流; 接收内部参考电流的负反馈单元，使电流镜像单元的RT端子连接端子和内部参考电流输出端子的电压相等，使内部参考电流恒定，并在IC电路内提供内部参考电流; 以及IC状态指示单元，其具有连接在RT端子和地之间与电流镜像单元进行互补操作的晶体管，并且通过与RT端子的互补操作相关联地向RT端子提供IC或系统的状态 当前镜像单元。

    Latency control circuit and semiconductor device including the circuit
    38.
    发明授权
    Latency control circuit and semiconductor device including the circuit 有权
    延迟控制电路和包括该电路的半导体器件

    公开(公告)号：US08837239B2

    公开(公告)日：2014-09-16

    申请号：US13797574

    申请日：2013-03-12

    Applicant: SK Hynix Inc. ,  University of Seoul Industry Cooperation Foundation

    Inventor： Jong Gon Jung ,  Yong Sam Moon ,  Yong Ju Kim ,  Jong Ho Jung

    IPC: G11C7/00 ,  G11C7/22

    CPC classification number: G11C7/222 ,  G11C2207/2272

    Abstract: A latency control circuit includes a clock delay configured to output a plurality of serial delay signals obtained by serially delaying an input clock signal with the same intervals, a deviation information generating unit configured to generate a deviation information on the basis of a delay value, which the clock signal undergoes in a chip, and latency information, a clock selector configured to output a plurality of clock selection signals based on the plurality of serial delay signals and the deviation information, a command signal processing unit configured to generate a read signal based on an input command signal, and output a variable delay duplication signal by variably delaying the read signal, and a latency shifter configured to output a latency signal by combining the plurality of clock selection signals with the variable delay duplication signal.

    Abstract translation: 延迟控制电路包括：时钟延迟，被配置为输出通过以相同间隔串行延迟输入时钟信号而获得的多个串行延迟信号;偏差信息生成单元，被配置为基于延迟值生成偏差信息， 时钟信号经历芯片，等待时间信息，时钟选择器，被配置为基于多个串行延迟信号和偏差信息输出多个时钟选择信号;命令信号处理单元，被配置为基于 输入命令信号，并通过可变地延迟读取信号来输出可变延迟复制信号;以及等待时间移位器，被配置为通过将多个时钟选择信号与可变延迟复制信号组合来输出等待时间信号。

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