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    MEMORY SYSTEM AND RELATED METHOD OF PROGRAMMING
    31.
    发明申请
    MEMORY SYSTEM AND RELATED METHOD OF PROGRAMMING 有权
    记忆系统及相关编程方法

    公开(公告)号：US20110032759A1

    公开(公告)日：2011-02-10

    申请号：US12832220

    申请日：2010-07-08

    Applicant: Yong June Kim ,  Jae hong Kim ,  Ki Jun Lee

    Inventor： Yong June Kim ,  Jae hong Kim ,  Ki Jun Lee

    IPC: G11C16/04

    CPC classification number: G11C11/5628 ,  G11C7/1012 ,  G11C11/5642 ,  G11C2211/5647

    Abstract: A method of programming a nonvolatile memory device comprises counting a number of state pairs in a unit of input data, modulating the unit of input data to reduce the number of state pairs contained therein, and programming the modulated unit of input data in the nonvolatile memory device. Each state pair comprises data with a first state and designated for programming in a memory cell connected to a first word line, and data with a second state and designated for programming in a memory cell connected to a second word line adjacent to the first word line. The memory cell connected to the first word line is adjacent to the memory cell connected to the second word line.

    Abstract translation: 一种对非易失性存储器件进行编程的方法包括以输入数据为单位对多个状态对进行计数，调制输入数据的单位以减少其中包含的状态对的数量，并将输入数据的调制单元编程在非易失性存储器 设备。 每个状态对包括具有第一状态并被指定用于在连接到第一字线的存储器单元中进行编程的数据，以及具有第二状态并被指定用于在连接到与第一字线相邻的第二字线的存储器单元中编程的数据 。 连接到第一字线的存储单元与连接到第二字线的存储单元相邻。

    Storage device and method for reading the same
    32.
    发明申请
    Storage device and method for reading the same 有权
    存储装置及其读取方法

    公开(公告)号：US20100302850A1

    公开(公告)日：2010-12-02

    申请号：US12662329

    申请日：2010-04-12

    Applicant: Yong June Kim ,  Heeseok Eun ,  Han Woong Yoo ,  Jaehong Kim ,  Hong Rak Son

    Inventor： Yong June Kim ,  Heeseok Eun ,  Han Woong Yoo ,  Jaehong Kim ,  Hong Rak Son

    IPC: G11C16/06 ,  G11C7/10 ,  G11C16/04

    CPC classification number: G11C16/26 ,  G06F11/1048 ,  G11C11/5642 ,  G11C16/0483 ,  G11C29/00

    Abstract: The storage device includes a storage unit configured to store data, an error controlling unit configured to correct an error of the data read out from the storage unit according to at least one read level, and a read level controlling unit configured to control the at least one read level when the error is uncorrectable. The read level controlling unit is configured to measure a distribution of memory cells of the storage unit, configured to filter the measured distribution, and configured to reset the at least one read level based on the filtered distribution.

    Abstract translation: 存储装置包括：被配置为存储数据的存储单元;错误控制单元，被配置为根据至少一个读取级别校正从存储单元读出的数据的错误;以及读取级别控制单元，被配置为至少控制 一个读取级别，当错误是不可校正的。 读取级别控制单元被配置为测量存储单元的存储器单元的分布，被配置为过滤所测量的分布，并且被配置为基于滤波的分布来重置所述至少一个读取级别。

    NONVOLATILE MEMORY DEVICE AND METHOD SYSTEM INCLUDING THE SAME
    33.
    发明申请
    NONVOLATILE MEMORY DEVICE AND METHOD SYSTEM INCLUDING THE SAME 审中-公开
    非易失性存储器件和包括其的方法系统

    公开(公告)号：US20100238705A1

    公开(公告)日：2010-09-23

    申请号：US12698720

    申请日：2010-02-02

    Applicant: Yong June Kim ,  Jaehong Kim ,  Junjin Kong

    Inventor： Yong June Kim ,  Jaehong Kim ,  Junjin Kong

    IPC: G11C11/00 ,  G11C7/00

    CPC classification number: G11C7/1006 ,  G11C7/1042 ,  G11C8/10 ,  G11C11/5628 ,  G11C11/5678 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2211/5623

    Abstract: A nonvolatile memory device performs interleaving of data to be stored in each wordline (memory page), or of data to be stored in multiple wordlines (memory pages). The NVM includes a memory cell array, a storage circuit of a de-interleaving circuit, and a read/write circuit. The storage circuit of the de-interleaving circuit is configured to store program data to be written interleaved into the memory cell array. The read/write circuit is configured to control the interleaved/deinterleaved data input/output between the memory cell array and the storage circuit. The write operation unit size may be the same or different from the read operation unit size. The storage circuit stores the program data of integer k times of a common divisor of a read operation unit size and a write operation unit size of the read/write circuit, wherein k may equal ‘m’ (the number of bits stored in each memory cell of the NVM).

    Abstract translation: 非易失性存储器件执行要存储在每个字线（存储器页）中的数据或要存储在多个字线（存储器页）中的数据的交织。 NVM包括存储单元阵列，解交织电路的存储电路和读/写电路。 解交织电路的存储电路被配置为将要被交织的程序数据存储到存储单元阵列中。 读/写电路被配置为控制存储单元阵列和存储电路之间的交错/去交织的数据输入/输出。 写入操作单元尺寸可以与读取操作单元尺寸相同或不同。 存储电路存储读/写电路的读操作单元大小和写操作单元大小的公约数的整数k倍的程序数据，其中k可以等于“m”（存储在每个存储器中的位数 NVM的单元）。

    DEVICE AND METHOD PROVIDING 1-BIT ERROR CORRECTION
    35.
    发明申请
    DEVICE AND METHOD PROVIDING 1-BIT ERROR CORRECTION 有权
    提供1位错误校正的设备和方法

    公开(公告)号：US20100174966A1

    公开(公告)日：2010-07-08

    申请号：US12651586

    申请日：2010-01-04

    Applicant: Yong June KIM ,  Jae Hong KIM ,  Jun Jin KONG

    Inventor： Yong June KIM ,  Jae Hong KIM ,  Jun Jin KONG

    IPC: H03M13/05 ,  G06F11/10

    CPC classification number: G06F11/1008 ,  H03M13/1105 ,  H03M13/1108

    Abstract: A 1-bit error correction method is provided. In the method, a variable node at which an error has occurred is detected based on a number of unsatisfied check nodes that do not satisfy a parity condition among check nodes connected to each of variable nodes and an error in a bit corresponding to the detected variable node is corrected.

    Abstract translation: 提供1位纠错方法。 在该方法中，基于在连接到每个可变节点的校验节点中不满足奇偶校验条件的不满足校验节点的数量和对应于检测变量的位的错误来检测发生错误的变量节点 节点被更正。

    Memory device and method of managing memory data error
    38.
    发明申请
    Memory device and method of managing memory data error 有权
    内存设备和管理内存数据错误的方法

    公开(公告)号：US20090287975A1

    公开(公告)日：2009-11-19

    申请号：US12453163

    申请日：2009-04-30

    Applicant: Yong June Kim ,  Jae Hong Kim ,  Jun Jin Kong ,  Kyoung Lae Cho

    Inventor： Yong June Kim ,  Jae Hong Kim ,  Jun Jin Kong ,  Kyoung Lae Cho

    IPC: G06F11/10 ,  G11C16/04 ,  G11C16/06 ,  G11C16/02 ,  H03M13/03

    CPC classification number: G11C16/10 ,  G06F11/1072 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/3454 ,  G11C29/00 ,  G11C2211/5621 ,  G11C2211/5634

    Abstract: Memory devices and/or methods of managing memory data errors are provided. A memory device detects and corrects an error bit of data read from a plurality of memory cells, and identifies a memory cell storing the detected error bit. The memory device assigns a verification voltage to each of the plurality of first memory cells, the assigned verification voltage corresponding to the corrected bit for the identified memory cell, the assigned verification voltage corresponding to the read data for the remaining memory cells. The memory device readjusts the data stored in the plurality of memory cells using the assigned verification voltage. Through this, it is possible to increase a retention period of the data of the memory device.

    Abstract translation: 提供了存储器件和/或管理存储器数据错误的方法。 存储器件检测并校正从多个存储器单元读取的数据的错误位，并且识别存储检测到的错误位的存储单元。 存储装置向多个第一存储器单元中的每一个分配验证电压，对应于所识别的存储单元的校正位的分配的验证电压，对应于剩余存储单元的读取数据的分配验证电压。 存储装置使用分配的验证电压重新调整存储在多个存储单元中的数据。 由此，可以增加存储装置的数据的保持期。

    Flash memory devices, data randomizing methods of the same, memory systems including the same
    40.
    发明授权
    Flash memory devices, data randomizing methods of the same, memory systems including the same 有权
    闪存设备，数据随机化方法相同，内存系统包括相同

    公开(公告)号：US08799593B2

    公开(公告)日：2014-08-05

    申请号：US13237350

    申请日：2011-09-20

    Applicant: Jung Soo Chung ,  Yong June Kim ,  Hong Rak Son ,  Jun Jin Kong

    Inventor： Jung Soo Chung ,  Yong June Kim ,  Hong Rak Son ,  Jun Jin Kong

    IPC: G06F13/28 ,  G06F12/02

    CPC classification number: G06F12/0246

    Abstract: Disclosed is a flash memory device which includes a memory cell array configured to store data, a randomizer configured to generate a random sequence, to interleave the random sequence using at least one of memory parameters associated with data to be programmed in the memory cell array, and a control logic circuit configured to provide the memory parameters to the randomizer and to control the randomizer.

    Abstract translation: 公开了一种闪速存储器件，其包括被配置为存储数据的存储器单元阵列，被配置为生成随机序列的随机器，以使用与要在存储器单元阵列中编程的数据相关联的存储器参数中的至少一个来交织随机序列， 以及控制逻辑电路，被配置为将所述存储器参数提供给所述随机发生器并且控制所述随机发生器。

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