公开(公告)号：US20100081015A1

公开(公告)日：2010-04-01

申请号：US12630449

申请日：2009-12-03

申请人： Hyungchan KIM ,  Hee gyu KIM ,  Yong-ho CHO ,  Jae sik CHUNG

发明人： Hyungchan KIM ,  Hee gyu KIM ,  Yong-ho CHO ,  Jae sik CHUNG

IPC分类号： H01M14/00 ,  H01M10/04

CPC分类号： H01M2/0404 ,  H01M2/34 ,  H01M10/0436 ,  H01M10/425 ,  H01M2200/10 ,  Y10T29/4911

摘要： An integral cap assembly comprising a top cap mounted as a base plate to an opening of a battery can and a cap subassembly including a protective circuit module and the like integrally mounted on the top cap, a method for manufacturing a secondary battery comprising the same, and a secondary battery manufactured thereby are disclosed. The cap assembly is provided as an integral member comprising the top cap acting as the base plate, and the cap subassembly having the protective circuit module provided thereon, thereby simplifying a manufacturing process of the battery while minimizing frequency of defective products. Additionally, the integral cap assembly is manufactured through insert injection molding, thereby providing notable advantages over the conventional technology.

摘要翻译： 一种整体盖组件，包括顶盖，其安装成电池罐的开口的基板，以及包括一体地安装在顶盖上的保护电路模块等的盖子组件，包括该顶盖的二次电池的制造方法， 并且公开了由此制造的二次电池。 帽组件设置为整体构件，其包括用作基板的顶盖，并且帽子组件具有设置在其上的保护电路模块，从而简化了电池的制造过程，同时使缺陷产品的频率最小化。 此外，通过插入式注射成型制造整体式盖组件，从而提供了超过常规技术的显着优点。

公开(公告)号：US20060160422A1

公开(公告)日：2006-07-20

申请号：US11285418

申请日：2005-11-22

申请人： Seunghyun Bang ,  Jaesik Chung ,  Yong-ho Cho

发明人： Seunghyun Bang ,  Jaesik Chung ,  Yong-ho Cho

IPC分类号： H01R24/00

CPC分类号： H01M2/204 ,  H01M2/10 ,  H01M2/266 ,  H01M10/425

摘要： An electrode connector includes a conductive wire and plates mounted on the wire such that the plates can be electrically connected to electrodes of cells. The plates are electrically connected to the wire. A battery module is manufactured with the electrode connector. The electrode connector is electrically connected to the electrodes of the cells by means of the plates. Consequently, the coupling of the electrode connector to the electrodes of the cells is easily accomplished by welding while damage to the cells is minimized. Furthermore, the electrical connection between the plates is accomplished by means of the flexible wire. Consequently, the assembly operation for the electrode connection is very easily carried out, and the electrode connector can be manufactured inexpensively.

摘要翻译： 电极连接器包括安装在电线上的导电线和板，使得板可以电连接到电池的电极。 板电连接到电线。 制造具有电极连接器的电池模块。 电极连接器通过板电连接到电池的电极。 因此，通过焊接容易地实现电极连接器与电池的电极的耦合，同时对电池的损坏最小化。 此外，板之间的电连接通过柔性线实现。 因此，电极连接的组装操作非常容易地进行，并且可以廉价地制造电极连接器。

公开(公告)号：US08185055B2

公开(公告)日：2012-05-22

申请号：US12042521

申请日：2008-03-05

申请人： Hyun Ho Choi ,  Hyo Sun Hwang ,  Tae In Hyon ,  Kyung Hun Jang ,  In Sun Lee ,  Hyun Gi Ahn ,  Yong Ho Cho ,  Dong Jo Park ,  Jung Hyun Park

发明人： Hyun Ho Choi ,  Hyo Sun Hwang ,  Tae In Hyon ,  Kyung Hun Jang ,  In Sun Lee ,  Hyun Gi Ahn ,  Yong Ho Cho ,  Dong Jo Park ,  Jung Hyun Park

IPC分类号： H04B1/00 ,  H04B15/00 ,  H04B17/00

CPC分类号： H04W16/14 ,  H04L27/2607 ,  H04L27/2647

摘要： An interference determination apparatus, including a signal receiver to receive a first signal of a primary network and a second signal of a secondary network; a correlator to compute a correlation value of a first cyclic prefix included in the first signal and a correlation value of a second cyclic prefix included in the second signal; and an interference determination unit to determine an interference level or whether the interference occurs between the primary network and the secondary network, using the correlation value of the first cyclic prefix and the correlation value of the second cyclic prefix.

摘要翻译： 一种干扰确定装置，包括用于接收主网络的第一信号的信号接收器和辅助网络的第二信号; 相关器，用于计算包括在第一信号中的第一循环前缀的相关值和包括在第二信号中的第二循环前缀的相关值; 以及干扰确定单元，使用第一循环前缀的相关值和第二循环前缀的相关值来确定干扰电平或者是否在主网络和次网之间发生干扰。

公开(公告)号：US20110032785A1

公开(公告)日：2011-02-10

申请号：US12820244

申请日：2010-06-22

申请人： Yong-Ho Cho

发明人： Yong-Ho Cho

IPC分类号： G11C8/08

CPC分类号： G11C8/08

摘要： A wordline driver includes a pre-driver, a sub-wordline driver and a transmission circuit. The pre-driver generates a wordline enable signal and a wordline disable signal based on one or more selection signals, a decoded address signal, and one or more timing control signals. The transmission circuit transmits the wordline enable signal and the wordline disable signal. The sub-wordline driver controls a voltage level of the sub-wordline based on the wordline enable signal and the wordline disable signal that are transmitted by the transmission circuit. Therefore, driving capacity may be improved.

摘要翻译： 字线驱动器包括预驱动器，子字线驱动器和发送电路。 预驱动器基于一个或多个选择信号，解码的地址信号和一个或多个定时控制信号产生字线使能信号和字线禁止信号。 发送电路发送字线使能信号和字线禁止信号。 子字线驱动器基于由发送电路发送的字线使能信号和字线禁止信号来控制子字线的电压电平。 因此，可以提高驾驶能力。

公开(公告)号：US07773435B2

公开(公告)日：2010-08-10

申请号：US12275692

申请日：2008-11-21

申请人： Yong-ho Cho

发明人： Yong-ho Cho

IPC分类号： G11C7/00 ,  G11C8/00 ,  G11C8/16

CPC分类号： G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/222

摘要： A semiconductor memory device includes a command buffer that receives an external command and outputs a first command signal, a clock buffer that receives an external clock signal and outputs a first internal clock signal, a delay measurement and initialization unit that receives the first internal clock signal and a fourth internal clock signal and responsively outputs a second internal clock signal and a plurality of delayed signals corresponding to a delay time between when the external clock signal is input and data is output, a delay locked loop that receives the second internal clock signal and outputs a third internal clock signal and the fourth internal clock signal, a latency signal generation unit that delays the first command signal by a delay time between when the second internal clock signal is input to the delay locked loop and when the third internal clock signal is output from the delay locked loop, and then outputs the delayed first command signal as a latency signal, in response to the second and third internal clock signals and the delayed signals, and a data output buffer that outputs the data in response to the latency signal and the third internal clock signal.

摘要翻译： 半导体存储器件包括：命令缓冲器，其接收外部命令并输出第一命令信号，时钟缓冲器，其接收外部时钟信号并输出​​第一内部时钟信号;延迟测量和初始化单元，其接收第一内部时钟信号 和第四内部时钟信号，并且响应于输出对应于输入外部时钟信号和输出数据之间的延迟时间的第二内部时钟信号和多个延迟信号;接收第二内部时钟信号的延迟锁定环;以及 输出第三内部时钟信号和第四内部时钟信号;等待时间信号生成单元，用于在第二内部时钟信号输入到延迟锁定环之间的延迟时间和第三内部时钟信号为 从延迟锁定环输出，然后输出延迟的第一命令信号作为等待时间信号， 响应于第二和第三内部时钟信号和延迟信号，以及数据输出缓冲器，其响应于等待时间信号和第三内部时钟信号输出数据。

公开(公告)号：US20090196112A1

公开(公告)日：2009-08-06

申请号：US12320625

申请日：2009-01-30

申请人： Yong-ho Cho

发明人： Yong-ho Cho

IPC分类号： G11C29/00 ,  G11C8/10

CPC分类号： G11C29/842 ,  G11C8/12

摘要： A block decoding circuit of a semiconductor memory device includes a plurality of block decoders, a plurality of repair address check circuits, a dummy repair address check circuit and a block selection signal generation circuit. The plurality of block decoders are configured to decode a received block selection address. The plurality of repair address check circuits are configured to generate second output signals based on whether a received block selection address and word line selection address are repair addresses. The dummy repair address check circuit is configured to generate a control signal in response to the block selection address and the word line selection address. The block selection signal generation circuit is configured to generate block selection signals based on the first output signals from the plurality of block decoders, the control signal from the dummy repair address circuit, and the second output signals from the repair address check circuits.

摘要翻译： 半导体存储器件的块解码电路包括多个块解码器，多个修复地址校验电路，虚拟修复地址校验电路和块选择信号生成电路。 多个块解码器被配置为对接收到的块选择地址进行解码。 多个修复地址检查电路被配置为基于接收的块选择地址和字线选择地址是修复地址来生成第二输出信号。 虚拟修复地址检查电路被配置为响应于块选择地址和字线选择地址而产生控制信号。 块选择信号生成电路被配置为基于来自多个块解码器的第一输出信号，来自虚拟修复地址电路的控制信号和来自修复地址检查电路的第二输出信号来生成块选择信号。

公开(公告)号：US20080204095A1

公开(公告)日：2008-08-28

申请号：US12027716

申请日：2008-02-07

申请人： Yong-ho Cho

发明人： Yong-ho Cho

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/4076 ,  G11C2207/2227

摘要： A method and apparatus for controlling a power-down mode of a delay locked loop (DLL), in which the apparatus includes a first switch unit, a DLL, and a second switch unit. The first switch unit transfers a first clock signal in response to a clock input enable signal. The DLL receives the first clock signal through the first switch unit to generate a second clock signal and is turned off by a power-down signal that is generated from the first clock signal latched by the first switch unit. The second switch unit transfers the second clock signal in response to a clock output enable signal. In a power-down mode, the clock input enable signal is deactivated in response to a clock enable signal and the clock output enable signal is deactivated after a predetermined number of clock cycles that are necessary for the latched first clock signal to be completely transferred through the delay cells of the DLL to an output terminal of the DLL. In a power-down exit mode, the power-down signal is deactivated in response to the clock enable signal and the clock input enable signal and the clock output enable signal are activated after a predetermined number of clock cycles that are necessary for the latched second clock signal to be completely transferred through the delay cells. Of the DLL to the output terminal of the DLL.

摘要翻译： 一种用于控制延迟锁定环（DLL）的掉电模式的方法和装置，其中该装置包括第一开关单元，DLL和第二开关单元。 第一开关单元响应于时钟输入使能信号传送第一时钟信号。 DLL通过第一开关单元接收第一时钟信号以产生第二时钟信号，并且由从第一开关单元锁存的第一时钟信号产生的掉电信号截止。 第二开关单元响应于时钟输出使能信号传送第二时钟信号。 在掉电模式下，时钟输入使能信号被响应于时钟使能信号被去激活，并且时钟输出使能信号在锁存的第一时钟信号必须被完全传送通过的预定数量的时钟周期之后被去激活 DLL的延迟单元到DLL的输出端。 在掉电退出模式中，响应于时钟使能信号，掉电信号被去激活，并且时钟输入使能信号和时钟输出使能信号在锁存的第二个所需的预定数量的时钟周期之后被激活 时钟信号通过延迟单元完全传输。 的DLL到DLL的输出端。

公开(公告)号：US20080192563A1

公开(公告)日：2008-08-14

申请号：US12010700

申请日：2008-01-29

申请人： Yong-ho Cho

发明人： Yong-ho Cho

IPC分类号： G11C8/18

CPC分类号： G11C8/18 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C2207/2272

摘要： Provided are a method and apparatus for controlling a read latency of a high-speed DRAM. A memory device may include a delay measurement unit, a delay locked loop, a latency counter and a data output buffer. The delay measurement unit measures a delay time between when an external clock signal is input and when read data is output to generate measurement signals and generates a first internal clock signal delayed from the external clock signal. The delay locked loop (DLL) receives the first internal clock signal and generates a second internal clock signal synchronized with the external clock signal. The latency counter generates a latency signal from an external read command signal in response to the measurement signals, and the data output buffer outputs the read data in response to the latency signal and the second internal clock signal.

摘要翻译： 提供了一种用于控制高速DRAM的读延迟的方法和装置。 存储器件可以包括延迟测量单元，延迟锁定环路，等待时间计数器和数据输出缓冲器。 延迟测量单元测量输入外部时钟信号和输出读取数据之间的延迟时间，以产生测量信号，并产生从外部时钟信号延迟的第一内部时钟信号。 延迟锁定环（DLL）接收第一内部时钟信号并产生与外部时钟信号同步的第二内部时钟信号。 延迟计数器响应于测量信号从外部读取命令信号产生等待时间信号，并且数据输出缓冲器响应等待时间信号和第二内部时钟信号输出读取的数据。

公开(公告)号：US20070154793A1

公开(公告)日：2007-07-05

申请号：US11566498

申请日：2006-12-04

申请人： Seunghyun BANG ,  Jaesik CHUNG ,  Yong-ho CHO

发明人： Seunghyun BANG ,  Jaesik CHUNG ,  Yong-ho CHO

IPC分类号： H01M2/24

CPC分类号： H01M2/204 ,  H01M2/10 ,  H01M2/266 ,  H01M10/425

摘要： Disclosed herein are an electrode connector including a conductive wire and a plurality of plates mounted on the wire such that the plates can be electrically connected to electrodes of cells, wherein the plates are electrically connected to the wire in a structure in which the plates are coupled to the wire by clamping, and a surface (A) of each plate contacting the wire is plated with the same metal (a) as the wire while a surface (B) of each plate connected to the corresponding electrode of each cell is plated with the same metal (b) as the corresponding electrode of each cell, and a battery module constructed with the electrode connector.

摘要翻译： 本文公开了一种电极连接器，其包括导线和安装在线上的多个板，使得板可以电连接到电池的电极，其中板以与板耦合的结构电连接到导线 通过夹持而接合到线上，并且与导线接触的每个板的表面（A）镀有与线相同的金属（a），同时连接到每个电池的相应电极的每个板的表面（B）镀有 与每个电池的相应电极相同的金属（b）和由电极连接器构成的电池模块。

公开(公告)号：US20060109911A1

公开(公告)日：2006-05-25

申请号：US11256188

申请日：2005-10-24

申请人： Euee-S Jang ,  Yung-Lyul Lee ,  Sun-Young Lee ,  Sung-Won Park ,  Jong-Woo Won ,  Yong-Ho Cho ,  Chung-Ku Lee

发明人： Euee-S Jang ,  Yung-Lyul Lee ,  Sun-Young Lee ,  Sung-Won Park ,  Jong-Woo Won ,  Yong-Ho Cho ,  Chung-Ku Lee

IPC分类号： H04N11/04 ,  H04N7/12 ,  H04B1/66 ,  H04N11/02

CPC分类号： H04N19/18 ,  H04N19/11 ,  H04N19/12 ,  H04N19/15 ,  H04N19/176 ,  H04N19/46 ,  H04N19/593 ,  H04N19/61

摘要： There are provided selective prediction encoding and decoding methods and selective prediction encoding and decoding devices. The selective prediction encoding device selects and performs one of an AC/DC prediction encoding method and an intra prediction encoding method which corresponds to the smaller of code amount from AC/DC prediction and an amount of AVC intra coding, records information indicating the selected encoding method in a header of a bit stream, and transmits the bit stream to the selective prediction decoding device. The selective prediction decoding device decodes the transmitted bit stream by the use of a decoding process corresponding to the information recorded in the header. Accordingly, it is possible to improve compression ratio and image quality by using the selective prediction encoding and decoding methods.

摘要翻译： 提供选择性预测编码和解码方法以及选择性预测编码和解码装置。 选择性预测编码装置选择并执行AC / DC预测编码方式和对应于AC / DC预测的代码量越小和AVC帧内编码量越小的帧内预测编码方式之一，记录表示选择编码的信息 方法，并将比特流发送到选择性预测解码装置。 选择性预测解码装置通过使用与记录在头部中的信息相对应的解码处理对发送的比特流进行解码。 因此，可以通过使用选择性预测编码和解码方法来提高压缩率和图像质量。