公开(公告)号：US20120292687A1

公开(公告)日：2012-11-22

申请号：US13433302

申请日：2012-03-29

Applicant: Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Chia-Hao Chang ,  Chia-Wei Chen

Inventor： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Chia-Hao Chang ,  Chia-Wei Chen

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7813 ,  H01L21/2255 ,  H01L21/2256 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/6659 ,  H01L29/66734 ,  H01L29/7811 ,  H01L2924/13091

Abstract: A super junction transistor includes a drain substrate, an epitaxial layer, wherein the epitaxial layer is disposed on the drain substrate, a plurality of gate structure units embedded on the surface of the epitaxial layer, a plurality of trenches disposed in the epitaxial layer between the drain substrate and the gate structure units, a buffer layer in direct contact with the inner surface of the trenches, a plurality of body diffusion regions with a first conductivity type adjacent to the outer surface of the trenches, wherein there is at least a PN junction on the interface between the body diffusion region and the epitaxial layer, and a doped source region, wherein the doped source region is disposed in the epitaxial layer and is adjacent to the gate structure unit.

Abstract translation: 超结晶体管包括漏极衬底，外延层，其中外延层设置在漏极衬底上，多个栅极结构单元嵌入在外延层的表面上，多个沟槽设置在外延层之间 漏极衬底和栅极结构单元，与沟槽的内表面直接接触的缓冲层，具有与沟槽的外表面相邻的第一导电类型的多个体扩散区，其中至少存在PN结 在体扩散区域和外延层之间的界面上，以及掺杂源极区域，其中掺杂源极区域设置在外延层中并且与栅极结构单元相邻。

公开(公告)号：US20120252176A1

公开(公告)日：2012-10-04

申请号：US13349038

申请日：2012-01-12

Applicant: Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Yi-Chun Shih

Inventor： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Yi-Chun Shih

IPC: H01L21/336

CPC classification number: H01L29/7802 ,  H01L21/2253 ,  H01L21/2255 ,  H01L29/0634 ,  H01L29/1095

Abstract: A method for fabricating a power transistor includes: (a) forming a trench in a substrate with a first electrical type; (b) diffusing second electrical type carriers into the substrate from the trench such that the substrate is formed into a first part and a second part that is diffused with the second electrical type carriers and that adjoins the trench, the first and second parts being crystal lattice continuous to each other; (c) forming a filling portion in the trench, the filling portion adjoining the second part; (d) performing a carrier-implanting process in the second part and the filling portion; and (e) forming over the substrate a gate structure that has a dielectric layer and a conductive layer.

Abstract translation: 一种制造功率晶体管的方法包括：（a）在第一电气类型的衬底中形成沟槽; （b）从沟槽将第二电气载体扩散到衬底中，使得衬底形成为第一部分，第二部分与第二电气型载流子扩散并邻接沟槽，第一和第二部分是晶体 格子相互连续; （c）在所述沟槽中形成填充部分，所述填充部分邻接所述第二部分; （d）在第二部分和填充部分中执行载体植入过程; 和（e）在衬底上形成具有电介质层和导电层的栅极结构。

公开(公告)号：US08178410B1

公开(公告)日：2012-05-15

申请号：US13171368

申请日：2011-06-28

Applicant: Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Jing-Qing Chan ,  Yi-Chun Shih

Inventor： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Jing-Qing Chan ,  Yi-Chun Shih

IPC: H01L21/8236

CPC classification number: H01L27/088 ,  H01L21/2255 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/7811

Abstract: A method for forming a power device includes the following steps. An epitaxial layer is formed on a substrate. A pad layer and hard mask are formed on the epitaxial layer. A trench is etched into the hard mask, the pad layer, and the epitaxial layer. The hard mask is removed. A buffer layer is formed on the sidewall of the trench. The trench is then filled with a dopant source layer comprising plural dopants. A drive-in process is performed to diffuse the dopants into the epitaxial layer through the buffer layer, thereby forming a diffusion region around the trench.

Abstract translation: 一种形成功率器件的方法包括以下步骤。 在衬底上形成外延层。 在外延层上形成焊盘层和硬掩模。 将沟槽蚀刻到硬掩模，焊盘层和外延层中。 硬面膜被去除。 缓冲层形成在沟槽的侧壁上。 然后用包括多个掺杂剂的掺杂剂源层填充沟槽。 执行驱入过程以通过缓冲层将掺杂剂扩散到外延层中，从而在沟槽周围形成扩散区域。

公开(公告)号：US20080284583A1

公开(公告)日：2008-11-20

申请号：US11749815

申请日：2007-05-17

Applicant: Yung-Fa Lin

Inventor： Yung-Fa Lin

IPC: G08B25/00

CPC classification number: G01C17/28

Abstract: An electronic compass, which uses an induction coil unit and action force generated from the earth's magnetic field to detect directions, is able to show data on a display panel. Since data on the display panel is reflected on the inclined plane ahead of the present invention, a driver driving on the road is able to look steadily at data reflected from this invention, so as to efficaciously reduce probability of traffic accidents due to observing data by lowering one's head. The induction coil unit described is easily understood compared with known techniques, thus the production cost is relatively low and this inexpensive invention can be popularly accepted on the market.

Abstract translation: 使用感应线圈单元和从地球磁场产生的作用力来检测方向的电子罗盘能够在显示面板上显示数据。 由于显示面板上的数据反映在本发明之前的倾斜平面上，所以在道路上驾驶的驾驶员能够稳定地看待本发明反映的数据，从而有效地降低了由于观察数据造成的交通事故的概率 降低头脑。 所描述的感应线圈单元与已知技术相比容易理解，因此生产成本相对较低，并且这种便宜的发明可以在市场上被普遍接受。

公开(公告)号：USD472868S1

公开(公告)日：2003-04-08

申请号：US29162550

申请日：2002-06-19

Applicant: Yung-Fa Lin

Designer： Yung-Fa Lin

公开(公告)号：US5929525A

公开(公告)日：1999-07-27

申请号：US110357

申请日：1998-07-06

Applicant: Yung-Fa Lin

Inventor： Yung-Fa Lin

IPC: H01L21/768 ,  H01L23/48 ,  H01L21/44

CPC classification number: H01L21/76834 ,  H01L21/76829 ,  H01L21/76838 ,  H01L21/76885 ,  H01L2924/0002

Abstract: A process for creating metal pillar via structures, used to interconnect multilevel metallizations, has been developed. The process features the creation of a via hole, in a thin dielectric layer, exposing the top surface of an underlying first level metallization structure. The metal pillar via structure is next formed, contacting the first level metallization structure, exposed in the opened via hole in the thin dielectric layer. The spaces between the metal pillar via structures are filled with a composite dielectric material, featuring a spin on glass layer, which provides partial planarazation. The planarazation process is completed via a chemical mechanical polishing process, which also exposes the top surface of the metal pillar via structure, making the metal pillar via structure easily accessible for contact for subsequent, overlying metallization structures.

Abstract translation: 已经开发了用于连接多层金属化的金属柱通孔结构的工艺。 该方法的特征在于在薄介电层中形成通孔，暴露下层第一级金属化结构的顶表面。 金属柱通孔结构接下来形成，与第一层金属化结构接触，暴露在薄介电层中的通孔中。 金属柱通孔结构之间的空间填充有复合电介质材料，其特征在于玻璃层上的自旋，其提供部分平面化。 平面化处理通过化学机械抛光工艺完成，化学机械抛光工艺也暴露了金属柱通孔结构的顶表面，使得金属柱通孔结构易于接近以用于随后的上覆金属化结构。

公开(公告)号：US5801093A

公开(公告)日：1998-09-01

申请号：US663573

申请日：1996-06-13

Applicant: Yung-Fa Lin

Inventor： Yung-Fa Lin

IPC: H01L21/768 ,  H01L21/44

CPC classification number: H01L21/76834 ,  H01L21/76829 ,  H01L21/76838 ,  H01L21/76885 ,  H01L2924/0002

Abstract: A process for creating metal pillar via structures, used to interconnect multilevel metallizations, has been developed. The process features the creation of a via hole, in a thin dielectric layer, exposing the top surface of an underlying first level metallization structure. The metal pillar via structure is next formed, contacting the first level metallization structure, exposed in the opened via hole in the thin dielectric layer. The spaces between the metal pillar via structures are filled with a composite dielectric material, featuring a spin on glass layer, which provides partial planarazation. The planarazation process is completed via a chemical mechanical polishing process, which also exposes the top surface of the metal pillar via structure, making the metal pillar via structure easily accessible for contact for subsequent, overlying metallization structures.

公开(公告)号：US20140063832A1

公开(公告)日：2014-03-06

申请号：US13604631

申请日：2012-09-06

Applicant: YUNG-FA LIN

Inventor： YUNG-FA LIN

IPC: F21V13/04 ,  F21V29/00

CPC classification number: F21S43/14 ,  B60Q1/0035 ,  B60Q1/0041 ,  B60Q1/0088 ,  B60Q1/0483 ,  B60Q1/20 ,  B60Q2400/30 ,  F21S41/147 ,  F21S41/663 ,  F21S45/47

Abstract: An LED lamp for car use can be mounted in a long strip-shaped installation position, comprises a case, a light-reflecting base, a light source series and a lens base. The case is mounted corresponding to the installation position and the case has an opening and a first fixing part mounted opposite to the opening for being connected securely to the light-reflecting base. The light-reflecting base has a plurality of reflectors. Each of the reflectors has a second fixing part for being connected securely to the light source series. The light source series has a plurality of first LED lights and a plurality of second LED lights. The lens base located at the opening wraps the opening. The LED lamp for car use of the present invention can be used as a fog light or a daytime running light, and save space for installation of lamps in a car.

Abstract translation: 用于汽车使用的LED灯可以安装在长的条形安装位置，包括壳体，光反射基座，光源系列和透镜基座。 壳体相对于安装位置安装，并且壳体具有开口和与开口相对安装的第一固定部分，以牢固地连接到光反射基座。 光反射基底具有多个反射器。 每个反射器具有用于牢固地连接到光源系列的第二固定部。 光源系列具有多个第一LED灯和多个第二LED灯。 位于开口处的透镜基座包裹开口。 本发明的汽车用LED灯可以用作雾灯或日间行车灯，并且节省了在汽车中安装灯具的空间。

公开(公告)号：US20130164915A1

公开(公告)日：2013-06-27

申请号：US13433282

申请日：2012-03-28

Applicant: Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Chia-Hao Chang

Inventor： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Chia-Hao Chang

IPC: H01L21/20

CPC classification number: H01L29/7813 ,  H01L29/0653 ,  H01L29/0886 ,  H01L29/456 ,  H01L29/66734

Abstract: A method for fabricating a power semiconductor device is provided. A substrate with a first conductivity type is prepared. A semiconductor layer with a second conductivity type is formed on the substrate. A hard mask pattern having at least an opening is formed on the semiconductor layer. A first trench etching is performed to form a first recess in the semiconductor layer via the opening. A first ion implantation is performed to vertically implant dopants into the bottom of the first recess via the opening, thereby forming a first doping region. A second trench etching is performed to etch through the first doping region, thereby forming a second recess.

Abstract translation: 提供一种制造功率半导体器件的方法。 制备具有第一导电类型的衬底。 在基板上形成具有第二导电类型的半导体层。 在半导体层上形成至少具有开口的硬掩模图案。 执行第一沟槽蚀刻以经由开口在半导体层中形成第一凹槽。 执行第一离子注入以通过开口垂直地将掺杂剂注入第一凹槽的底部，从而形成第一掺杂区域。 执行第二沟槽蚀刻以蚀刻穿过第一掺杂区域，从而形成第二凹槽。

公开(公告)号：US20130119460A1

公开(公告)日：2013-05-16

申请号：US13543877

申请日：2012-07-08

Applicant: Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Chia-Hao Chang ,  Chia-Wei Chen

Inventor： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Chia-Hao Chang ,  Chia-Wei Chen

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/0634 ,  H01L21/2255 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/423 ,  H01L29/66348 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813

Abstract: The present invention provides a trench type power transistor device including a substrate, an epitaxial layer, a doped diffusion region, a doped source region, and a gate structure. The substrate, the doped diffusion region, and the doped source region have a first conductivity type, and the substrate has an active region and a termination region. The epitaxial layer is disposed on the substrate, and has a second conductivity type. The epitaxial layer has a through hole disposed in the active region. The doped diffusion region is disposed in the epitaxial layer at a side of the through hole, and is in contact with the substrate. The doped source region is disposed in the epitaxial layer disposed right on the doped diffusion region, and the gate structure is disposed in the through hole between the doped diffusion region and the doped source region.

Abstract translation: 本发明提供一种沟槽型功率晶体管器件，其包括衬底，外延层，掺杂扩散区域，掺杂源极区域和栅极结构。 衬底，掺杂扩散区和掺杂源区具有第一导电类型，并且衬底具有有源区和端接区。 外延层设置在基板上，并具有第二导电类型。 外延层具有设置在有源区中的通孔。 掺杂扩散区域设置在通孔一侧的外延层中，并与衬底接触。 掺杂源极区域设置在垂直于掺杂扩散区域的外延层中，栅极结构设置在掺杂扩散区域和掺杂源极区域之间的通孔中。