公开(公告)号：US08541278B2

公开(公告)日：2013-09-24

申请号：US13234132

申请日：2011-09-15

Applicant: Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Yi-Chun Shih

Inventor： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Yi-Chun Shih

IPC: H01L21/336

CPC classification number: H01L29/66666 ,  H01L21/2255 ,  H01L21/2256 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/7811 ,  H01L29/7813

Abstract: A method for fabricating a super-junction semiconductor power device with reduced Miller capacitance includes the following steps. An N-type substrate is provided and a P-type epitaxial layer is formed on the N-type substrate. At least a trench is formed in the P-type epitaxial layer followed by forming a buffer layer on interior surface in the trench. An N-type dopant layer is filled into the trench and then the N-type dopant layer is etched to form a recessed structure at an upper portion of the trench. A gate oxide layer is formed, and simultaneously, dopants in the N-type dopant layer diffuse into the P-type epitaxial layer, forming an N-type diffusion layer. Finally, a gate conductor is filled into the recessed structure and an N-type source doped region is formed around the gate conductor in the P-type epitaxial layer.

公开(公告)号：US08536003B2

公开(公告)日：2013-09-17

申请号：US13211304

申请日：2011-08-17

Applicant: Yung-Fa Lin ,  Shou-Yi Hsu ,  Yi-Lin Sun

Inventor： Yung-Fa Lin ,  Shou-Yi Hsu ,  Yi-Lin Sun

IPC: H01L21/8238

CPC classification number: H01L21/2257 ,  H01L29/04 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/7811

Abstract: A method for fabricating a semiconductor power device includes the following steps. First, a substrate having thereon at least a semiconductor layer and a pad layer is provided. Then, at least a trench is etched into the pad layer and the semiconductor layer followed by depositing a dopant source layer in the trench and on the pad layer. A process is carried out thermally driving in dopants of the dopant source layer into the semiconductor layer. A rapid thermal process is performed to mend defects in the dopant source layer and defects between the dopant source layer and the semiconductor layer. Finally, a polishing process is performed to remove the dopant source layer from a surface of the pad layer.

Abstract translation: 一种制造半导体功率器件的方法包括以下步骤。 首先，提供其上具有至少半导体层和衬垫层的衬底。 然后，将至少一个沟槽蚀刻到衬垫层和半导体层中，随后在沟槽和衬垫层中沉积掺杂剂源层。 对掺杂剂源层的掺杂剂进行半导体层的热驱动。 进行快速热处理以修补掺杂剂源层中的缺陷和掺杂剂源层和半导体层之间的缺陷。 最后，进行抛光处理以从衬垫层的表面去除掺杂剂源层。

公开(公告)号：US20130203229A1

公开(公告)日：2013-08-08

申请号：US13537080

申请日：2012-06-29

Applicant: Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Chia-Hao Chang

Inventor： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Chia-Hao Chang

IPC: H01L21/336 ,  H01L21/322

CPC classification number: H01L29/7802 ,  H01L21/02238 ,  H01L21/2255 ,  H01L21/30604 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66727

Abstract: The present invention provides a method of reducing a surface doping concentration of a doped diffusion region. First, a semiconductor substrate is provided. The semiconductor substrate has the doped diffusion region disposed therein, and the doped diffusion region is in contact with a surface of the semiconductor substrate. A doping concentration of the doped diffusion region close to the surface is larger than a doping concentration of the doped diffusion region away from the surface. Then, a thermal oxidation process is performed to form an oxide layer on the surface of the semiconductor substrate. A part of the doped diffusion region in contact with the surface reacts with oxygen to form a part of the oxide layer. Then, the oxide layer is removed.

Abstract translation: 本发明提供了降低掺杂扩散区域的表面掺杂浓度的方法。 首先，提供半导体基板。 半导体衬底具有设置在其中的掺杂扩散区，并且掺杂扩散区与半导体衬底的表面接触。 接近表面的掺杂扩散区域的掺杂浓度大于掺杂扩散区域远离表面的掺杂浓度。 然后，进行热氧化处理，以在半导体衬底的表面上形成氧化物层。 与表面接触的掺杂扩散区的一部分与氧反应形成氧化物层的一部分。 然后，除去氧化物层。

公开(公告)号：US20130153994A1

公开(公告)日：2013-06-20

申请号：US13556166

申请日：2012-07-23

Applicant: Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Chia-Hao Chang

Inventor： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Chia-Hao Chang

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/66734 ,  H01L21/26586 ,  H01L27/088 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/6653 ,  H01L29/7813

Abstract: The present invention provides a manufacturing method of a trench type power transistor device with a super junction. First, a substrate of a first conductivity type is provided, and then an epitaxial layer of a second conductive type is formed on the substrate. Next, a through hole is formed in the epitaxial layer, and the through hole penetrates through the epitaxial layer. Two doped drain regions of the first conductivity type are then formed in the epitaxial layer respectively at two sides of the through hole, and the doped drain regions extend from a top surface of the epitaxial layer to be in contact with the substrate.

Abstract translation: 本发明提供一种具有超结的沟槽型功率晶体管器件的制造方法。 首先，提供第一导电类型的衬底，然后在衬底上形成第二导电类型的外延层。 接下来，在外延层中形成通孔，并且通孔穿过外延层。 然后分别在通孔的两侧在外延层中形成第一导电类型的两个掺杂漏极区，并且掺杂漏极区从外延层的顶表面延伸以与衬底接触。

公开(公告)号：US20130043528A1

公开(公告)日：2013-02-21

申请号：US13451557

申请日：2012-04-20

Applicant: Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Chia-Hao Chang ,  Chia-Wei Chen

Inventor： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Chia-Hao Chang ,  Chia-Wei Chen

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7827 ,  H01L21/2255 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

Abstract: The present invention provides a power transistor device including a substrate, a first epitaxial layer, a doped diffusion region, a second epitaxial layer, a doped base region, and a doped source region. The substrate, the first epitaxial layer, the second epitaxial layer and the doped source region have a first conductive type, and the doped diffusion region and the doped base region have a second conductive type. The first epitaxial layer and the second epitaxial layer are sequentially disposed on the substrate, and the doped diffusion region is disposed in the first epitaxial layer. The doped base region is disposed in the second epitaxial layer and contacts the doped diffusion region, and the doped source region is disposed in the doped base region. A doping concentration of the second epitaxial layer is less than a doping concentration of the first epitaxial layer.

Abstract translation: 本发明提供一种功率晶体管器件，其包括衬底，第一外延层，掺杂扩散区，第二外延层，掺杂基极区和掺杂源极区。 衬底，第一外延层，第二外延层和掺杂源极区域具有第一导电类型，并且掺杂扩散区域和掺杂基极区域具有第二导电类型。 第一外延层和第二外延层依次设置在基板上，掺杂扩散区域设置在第一外延层中。 掺杂基区设置在第二外延层中并与掺杂扩散区接触，并且掺杂源区设置在掺杂基区中。 第二外延层的掺杂浓度小于第一外延层的掺杂浓度。

公开(公告)号：US20100284196A1

公开(公告)日：2010-11-11

申请号：US12436145

申请日：2009-05-06

Applicant: Yung-Fa Lin

Inventor： Yung-Fa Lin

IPC: B60Q1/26

CPC classification number: B60Q1/323

Abstract: A vehicle door safety warning lamp is provided. A light source is respectively disposed on each side of a light socket, and each light source is electrically connected to a power supply device of a vehicle. A white or transparent first shade body and a colored (for example, red or yellow) second shade body cover the two sides of the light socket. When a vehicle door is opened, the light sources disposed on the two sides of the light socket emit lights at the same time, light rays from the first shade body are used to irradiate a traveling path of passengers, and light rays from the second shade body are used to warn other vehicles at the back, thereby improving the safety of the passengers when getting on and off the passenger vehicles (for example, buses or touring vehicles).

Abstract translation: 提供车门安全警示灯。 光源分别设置在灯座的每一侧，并且每个光源电连接到车辆的电源装置。 白色或透明的第一个遮光罩和彩色（例如红色或黄色）第二个遮光罩遮盖灯座的两侧。 当车门打开时，设置在灯座两侧的光源同时发光，来自第一遮阳体的光线用于照射乘客的行进路径，并且来自第二帘子的光线 身体用于警告后方的其他车辆，从而提高乘客在乘客车辆（例如公共汽车或旅游车辆）上的安全性。

公开(公告)号：US20090294750A1

公开(公告)日：2009-12-03

申请号：US12325067

申请日：2008-11-28

Applicant: Jen-Chi Chuang ,  Yung-Fa Lin ,  Ming-Jeng Huang

Inventor： Jen-Chi Chuang ,  Yung-Fa Lin ,  Ming-Jeng Huang

IPC: H01L45/00

CPC classification number: H01L45/144 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/124 ,  H01L45/126 ,  H01L45/148 ,  H01L45/1691

Abstract: An exemplary phase change memory device is provided, including a substrate with a first electrode formed thereover. A first dielectric layer is formed over the first electrode and the substrate. A plurality of cup-shaped heating electrodes is respectively disposed in a portion of the first dielectric layer. A first insulating layer is formed over the first dielectric layer, partially covering the cup-shaped heating electrodes and the first dielectric layer therebetween. A second insulating layer is formed over the first dielectric layer, partially covering the cup-shaped heating electrodes and the first dielectric layer therebetween. A pair of phase change material layers is respectively disposed on opposing sidewalls of the second insulating layer and contacting with one of the cup-shaped heating electrodes. A pair of first conductive layers is formed on the second insulating layer along the second direction, respectively.

Abstract translation: 提供了一种示例性相变存储器件，包括其上形成有第一电极的衬底。 第一电介质层形成在第一电极和衬底之上。 多个杯形加热电极分别设置在第一电介质层的一部分中。 在第一电介质层上形成第一绝缘层，部分覆盖杯形加热电极和第一绝缘层之间的第一介电层。 在第一电介质层上形成第二绝缘层，部分覆盖杯形加热电极和第一绝缘层之间的第一介电层。 一对相变材料层分别设置在第二绝缘层的相对的侧壁上并与杯形加热电极之一接触。 一对第一导电层分别沿第二方向形成在第二绝缘层上。

公开(公告)号：US20090146127A1

公开(公告)日：2009-06-11

申请号：US12135041

申请日：2008-06-06

Applicant: Ming-Jeng Huang ,  Yung-Fa Lin

Inventor： Ming-Jeng Huang ,  Yung-Fa Lin

IPC: H01L47/00

CPC classification number: H01L27/2436 ,  G11C13/0004 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

Abstract: Phase change memories comprising a top electrode, a phase change element, a plurality of via holes allocated between the top electrode and the phase change element, at least four heaters aiming at different regions of the phase change element, and a plurality of bottom electrodes and transistors corresponding to the heaters. The bottom electrodes are respectively coupled to the heaters. Regarding the transistors, their first terminals are respectively coupled to the bottom electrodes, their control terminals are used for coupling to word lines, and their second terminals are used for coupling to bit lines. In an embodiment with four heaters, the regions the heaters aimed at the phase change element form a 2×2 storage array.

Abstract translation: 相变存储器，包括顶电极，相变元件，分配在顶电极和相变元件之间的多个通孔，至少四个对准相变元件的不同区域的加热器，以及多个底电极和 对应于加热器的晶体管。 底部电极分别连接到加热器。 关于晶体管，它们的第一端子分别耦合到底部电极，它们的控制端子用于耦合到字线，并且它们的第二端子用于耦合到位线。 在具有四个加热器的实施例中，加热器瞄准相变元件的区域形成2x2存储阵列。

公开(公告)号：US07540640B2

公开(公告)日：2009-06-02

申请号：US12167577

申请日：2008-07-03

Applicant: Yung-Fa Lin

Inventor： Yung-Fa Lin

IPC: B60Q1/00

CPC classification number: B60Q1/32 ,  B60Q1/2607 ,  B60Q1/2696 ,  B60Q1/52 ,  F21V33/0076 ,  F21Y2115/10

Abstract: An illuminating warning lamp includes a first light source and a second light source assembled on a lamp socket. An irradiation direction of the first light source and that of the second light source form an angle of 90 degrees with respect to each other. Additionally, a first lamp casing for encapsulating the first light source is further formed with a through hole at one side thereof, and a second lamp casing corresponding to the second light source is assembled within the through hole. After the first and second light sources are both driven to emit lights, the lamp simultaneously emits warning lights and illumination light.

Abstract translation: 照明警告灯包括组装在灯座上的第一光源和第二光源。 第一光源和第二光源的照射方向彼此相差90度。 此外，用于密封第一光源的第一灯壳还在其一侧形成有通孔，并且与通孔相对应的第二灯壳组装在第二光源中。 在第一和第二光源都被驱动发光后，灯同时发出警告灯和照明灯。

公开(公告)号：US5897374A

公开(公告)日：1999-04-27

申请号：US869021

申请日：1997-06-04

Applicant: Yung-Fa Lin

Inventor： Yung-Fa Lin

IPC: H01L21/768 ,  H01L21/44

CPC classification number: H01L21/76804

Abstract: A new method of metallization of an integrated circuit is described. A dielectric layer is provided over a first conducting layer over an insulating layer over a semiconductor substrate. The dielectric layer is covered with a layer of photoresist which is patterned to provide a photoresist mask. At least one via hole is etched through the dielectric layer to the first conducting layer. The photoresist mask is removed. The via hole is etched through the first conducting layer resulting in an undercutting of the dielectric layer. The exposed surfaces of the first conducting layer are cleaned. The insulating layer overhang protects the exposed surfaces from damage or contamination. A second conducting layer is deposited over the surface of the dielectric layer and within the via hole completing the metallization in the fabrication of the integrated circuit.

Abstract translation: 描述了集成电路的金属化的新方法。 在半导体衬底上的绝缘层上方的第一导电层上提供电介质层。 介电层被一层光致抗蚀剂覆盖，该层被图案化以提供光致抗蚀剂掩模。 至少一个通孔通过介电层蚀刻到第一导电层。 去除光致抗蚀剂掩模。 通孔穿过第一导电层被蚀刻，导致电介质层的底切。 清洁第一导电层的暴露表面。 绝缘层悬垂保护暴露的表面免受损坏或污染。 第二导电层沉积在电介质层的表面上并且在通孔内沉积，从而在集成电路的制造中完成金属化。