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    POWER TRANSISTOR DEVICE AND MANUFACTURING METHOD THEREOF
    3.
    发明申请
    POWER TRANSISTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
    功率晶体管器件及其制造方法

    公开(公告)号：US20130105891A1

    公开(公告)日：2013-05-02

    申请号：US13533957

    申请日：2012-06-26

    申请人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Chia-Hao Chang ,  Chia-Wei Chen

    发明人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Chia-Hao Chang ,  Chia-Wei Chen

    IPC分类号： H01L21/336 ,  H01L29/78

    CPC分类号： H01L29/7827 ,  H01L21/2255 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0869 ,  H01L29/0886 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

    摘要： The present invention provides a power transistor device including a substrate, an epitaxial layer, a dopant source layer, a doped drain region, a first insulating layer, a gate structure, a second insulating layer, a doped source region, and a metal layer. The substrate, the doped drain region, and the doped source region have a first conductive type, while the epitaxial layer has a second conductive type. The epitaxial layer is formed on the substrate and has at least one through hole through the epitaxial layer. The first insulating layer, the gate structure, and the second insulating layer are formed sequentially on the substrate in the through hole. The doped drain region and doped source region are formed in the epitaxial layer at one side of the through hole. The metal layer is formed on the epitaxial layer and extends into the through hole to contact the doped source region.

    摘要翻译： 本发明提供一种功率晶体管器件，其包括衬底，外延层，掺杂剂源层，掺杂漏极区，第一绝缘层，栅极结构，第二绝缘层，掺杂源极区和金属层。 衬底，掺杂漏极区域和掺杂源极区域具有第一导电类型，而外延层具有第二导电类型。 外延层形成在衬底上并且具有穿过外延层的至少一个通孔。 第一绝缘层，栅极结构和第二绝缘层依次形成在通孔中的基板上。 掺杂漏极区域和掺杂源极区域形成在通孔一侧的外延层中。 金属层形成在外延层上并延伸到通孔中以与掺杂源极区接触。

    Power transistor device and fabricating method thereof
    4.
    发明申请
    Power transistor device and fabricating method thereof 审中-公开
    功率晶体管器件及其制造方法

    公开(公告)号：US20130043528A1

    公开(公告)日：2013-02-21

    申请号：US13451557

    申请日：2012-04-20

    申请人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Chia-Hao Chang ,  Chia-Wei Chen

    发明人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Chia-Hao Chang ,  Chia-Wei Chen

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7827 ,  H01L21/2255 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

    摘要： The present invention provides a power transistor device including a substrate, a first epitaxial layer, a doped diffusion region, a second epitaxial layer, a doped base region, and a doped source region. The substrate, the first epitaxial layer, the second epitaxial layer and the doped source region have a first conductive type, and the doped diffusion region and the doped base region have a second conductive type. The first epitaxial layer and the second epitaxial layer are sequentially disposed on the substrate, and the doped diffusion region is disposed in the first epitaxial layer. The doped base region is disposed in the second epitaxial layer and contacts the doped diffusion region, and the doped source region is disposed in the doped base region. A doping concentration of the second epitaxial layer is less than a doping concentration of the first epitaxial layer.

    摘要翻译： 本发明提供一种功率晶体管器件，其包括衬底，第一外延层，掺杂扩散区，第二外延层，掺杂基极区和掺杂源极区。 衬底，第一外延层，第二外延层和掺杂源极区域具有第一导电类型，并且掺杂扩散区域和掺杂基极区域具有第二导电类型。 第一外延层和第二外延层依次设置在基板上，掺杂扩散区域设置在第一外延层中。 掺杂基区设置在第二外延层中并与掺杂扩散区接触，并且掺杂源区设置在掺杂基区中。 第二外延层的掺杂浓度小于第一外延层的掺杂浓度。

    TRENCH TYPE POWER TRANSISTOR DEVICE AND FABRICATING METHOD THEREOF
    5.
    发明申请
    TRENCH TYPE POWER TRANSISTOR DEVICE AND FABRICATING METHOD THEREOF 有权
    TRENCH型功率晶体管器件及其制造方法

    公开(公告)号：US20130119460A1

    公开(公告)日：2013-05-16

    申请号：US13543877

    申请日：2012-07-08

    申请人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Chia-Hao Chang ,  Chia-Wei Chen

    发明人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Chia-Hao Chang ,  Chia-Wei Chen

    IPC分类号： H01L21/336 ,  H01L29/78

    CPC分类号： H01L29/0634 ,  H01L21/2255 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/423 ,  H01L29/66348 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813

    摘要： The present invention provides a trench type power transistor device including a substrate, an epitaxial layer, a doped diffusion region, a doped source region, and a gate structure. The substrate, the doped diffusion region, and the doped source region have a first conductivity type, and the substrate has an active region and a termination region. The epitaxial layer is disposed on the substrate, and has a second conductivity type. The epitaxial layer has a through hole disposed in the active region. The doped diffusion region is disposed in the epitaxial layer at a side of the through hole, and is in contact with the substrate. The doped source region is disposed in the epitaxial layer disposed right on the doped diffusion region, and the gate structure is disposed in the through hole between the doped diffusion region and the doped source region.

    摘要翻译： 本发明提供一种沟槽型功率晶体管器件，其包括衬底，外延层，掺杂扩散区域，掺杂源极区域和栅极结构。 衬底，掺杂扩散区和掺杂源区具有第一导电类型，并且衬底具有有源区和端接区。 外延层设置在基板上，并具有第二导电类型。 外延层具有设置在有源区中的通孔。 掺杂扩散区域设置在通孔一侧的外延层中，并与衬底接触。 掺杂源极区域设置在垂直于掺杂扩散区域的外延层中，栅极结构设置在掺杂扩散区域和掺杂源极区域之间的通孔中。

    Manufacturing method of power transistor device
    6.
    发明授权
    Manufacturing method of power transistor device 有权
    功率晶体管器件的制造方法

    公开(公告)号：US08524559B2

    公开(公告)日：2013-09-03

    申请号：US13533957

    申请日：2012-06-26

    申请人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Chia-Hao Chang ,  Chia-Wei Chen

    发明人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Chia-Hao Chang ,  Chia-Wei Chen

    IPC分类号： H01L21/336 ,  H01L21/22 ,  H01L21/38

    CPC分类号： H01L29/7827 ,  H01L21/2255 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0869 ,  H01L29/0886 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

    摘要： The present invention provides a power transistor device including a substrate, an epitaxial layer, a dopant source layer, a doped drain region, a first insulating layer, a gate structure, a second insulating layer, a doped source region, and a metal layer. The substrate, the doped drain region, and the doped source region have a first conductive type, while the epitaxial layer has a second conductive type. The epitaxial layer is formed on the substrate and has at least one through hole through the epitaxial layer. The first insulating layer, the gate structure, and the second insulating layer are formed sequentially on the substrate in the through hole. The doped drain region and doped source region are formed in the epitaxial layer at one side of the through hole. The metal layer is formed on the epitaxial layer and extends into the through hole to contact the doped source region.

    摘要翻译： 本发明提供一种功率晶体管器件，其包括衬底，外延层，掺杂剂源层，掺杂漏极区，第一绝缘层，栅极结构，第二绝缘层，掺杂源极区和金属层。 衬底，掺杂漏极区域和掺杂源极区域具有第一导电类型，而外延层具有第二导电类型。 外延层形成在衬底上并且具有穿过外延层的至少一个通孔。 第一绝缘层，栅极结构和第二绝缘层依次形成在通孔中的基板上。 掺杂漏极区域和掺杂源极区域形成在通孔一侧的外延层中。 金属层形成在外延层上并延伸到通孔中以与掺杂源极区接触。

    Method for fabricating Schottky device
    7.
    发明授权
    Method for fabricating Schottky device 有权
    制造肖特基器件的方法

    公开(公告)号：US08466051B2

    公开(公告)日：2013-06-18

    申请号：US13338256

    申请日：2011-12-28

    申请人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Chia-Hao Chang ,  Chia-Wei Chen

    发明人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Chia-Hao Chang ,  Chia-Wei Chen

    IPC分类号： H01L21/338 ,  H01L29/812

    CPC分类号： H01L21/22 ,  H01L21/2254 ,  H01L21/2256 ,  H01L21/2257 ,  H01L21/2652 ,  H01L21/28 ,  H01L29/66143 ,  H01L29/872

    摘要： A method for fabricating a Schottky device includes the following sequences. First, a substrate with a first conductivity type is provided and an epitaxial layer with the first conductivity type is grown on the substrate. Then, a patterned dielectric layer is formed on the epitaxial layer, and a metal silicide layer is formed on a surface of the epitaxial layer. A dopant source layer with a second conductivity type is formed on the metal silicide layer, followed by applying a thermal drive-in process to diffuse the dopants inside the dopant source layer into the epitaxial layer. Finally, a conductive layer is formed on the metal silicide layer.

    摘要翻译： 制造肖特基器件的方法包括以下顺序。 首先，提供具有第一导电类型的衬底，并且在衬底上生长具有第一导电类型的外延层。 然后，在外延层上形成图案化的介电层，在外延层的表面上形成金属硅化物层。 在金属硅化物层上形成具有第二导电类型的掺杂剂源层，随后施加热驱动工艺以将掺杂剂源层内的掺杂剂扩散到外延层中。 最后，在金属硅化物层上形成导电层。

    SEMICONDUCTOR POWER DEVICE
    10.
    发明申请
    SEMICONDUCTOR POWER DEVICE 有权
    半导体功率器件

    公开(公告)号：US20120306006A1

    公开(公告)日：2012-12-06

    申请号：US13227472

    申请日：2011-09-07

    申请人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Yi-Chun Shih

    发明人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Yi-Chun Shih

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7811 ,  H01L21/2255 ,  H01L29/0634 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/7803 ,  H01L29/7809

    摘要： A semiconductor power device includes a substrate, a first semiconductor layer on the substrate, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer. At least a recessed epitaxial structure is disposed within a cell region and the recessed epitaxial structure may be formed in a pillar or stripe shape. A first vertical diffusion region is disposed in the third semiconductor layer and the recessed epitaxial structure is surrounded by the first vertical diffusion region. A source conductor is disposed on the recessed epitaxial structure and a trench isolation is disposed within a junction termination region surrounding the cell region. In addition, the trench isolation includes a trench, a first insulating layer on an interior surface of the trench, and a conductive layer filled into the trench, wherein the source conductor connects electrically with the conductive layer.

    摘要翻译： 半导体功率器件包括衬底，衬底上的第一半导体层，第一半导体层上的第二半导体层以及第二半导体层上的第三半导体层。 至少凹入的外延结构设置在单元区域内，并且凹入的外延结构可以形成为柱状或条形。 第一垂直扩散区域设置在第三半导体层中，并且凹入的外延结构被第一垂直扩散区域包围。 源极导体设置在凹陷的外延结构上，并且沟槽隔离设置在围绕电池区的连接终端区域内。 此外，沟槽隔离包括沟槽，在沟槽的内表面上的第一绝缘层和填充到沟槽中的导电层，其中源极导体与导电层电连接。