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    Systems and Methods of Power Management
    34.
    发明申请
    Systems and Methods of Power Management 有权

    公开(公告)号：US20210208803A1

    公开(公告)日：2021-07-08

    申请号：US16735606

    申请日：2020-01-06

    Applicant: Arm Limited

    Inventor： James Edward Myers ,  Pranay Prabhat ,  Matthew James Walker ,  Parameshwarappa Anand Kumar Savanth ,  Fernando Garcia Redondo

    IPC: G06F3/06 ,  G06F1/3234 ,  G06F1/3221 ,  G06F1/3209

    Abstract: According to one implementation of the present disclosure, a method for power management is disclosed. The method includes: computing, by a central processing unit, software instructions of a software workload in an active-mode operation corresponding to a first operating point on a performance curve of a performance mode; transitioning from instances of the active-mode operation to instances of standby-mode operation of the CPU, and recording, by a time tracking element, each of a plurality of standby entry data points; transitioning from the instances of the standby-mode operation to the instances of the active-mode operation of the CPU, and recording, by the time tracking element, each of a plurality of standby exit data points; and determining a second operating point on the performance curve of the performance mode based on the recorded standby entry data points and the recorded standby exit data points.

    Adapting the usage configuration of integrated circuit input-output pads
    35.
    发明授权
    Adapting the usage configuration of integrated circuit input-output pads 有权

    公开(公告)号：US10996269B2

    公开(公告)日：2021-05-04

    申请号：US15533479

    申请日：2015-12-22

    Applicant: ARM LIMITED

    Inventor： James Edward Myers ,  Parameshwarappa Anand Kumar Savanth

    IPC: G01R31/28 ,  G01R31/317 ,  G06F11/27

    Abstract: Techniques for implementing a self-test procedure of an integrated circuit are provided, where the self-test procedure comprises testing for an electrical connection between first and second input-output pads of the integrated circuit. A control device is capable of adapting a functional configuration of usage of the first and second input-output pads in dependence on presence of the electrical connection. A corresponding integrated circuit, printed circuit and method are also provided. These techniques allow the integrated circuit to be used in a variety of contexts, without requiring physical customisation of the integrated circuit to adapt it to its usage context, in particular where connections from the context to the pads of the integrated circuit may be made to individual pads in some contexts or may span more than one pad in other contexts.

    Digital forward body biasing in CMOS circuits
    37.
    发明授权
    Digital forward body biasing in CMOS circuits 有权

    公开(公告)号：US10181848B2

    公开(公告)日：2019-01-15

    申请号：US15418331

    申请日：2017-01-27

    Applicant: ARM Limited

    Inventor： Pranay Prabhat ,  Parameshwarappa Anand Kumar Savanth ,  James Edward Myers

    IPC: H03K17/687 ,  H01L29/10

    Abstract: Embodiments are described for digital forward body biasing CMOS circuits. In an embodiment, a power management unit limits the amount of time for which digital forward body biasing may be implemented. In another embodiment, once a CMOS circuit is put into a full digital forward body bias mode, the CMOS circuit is gradually brought back to a zero forward body bias mode. In another embodiment, charge is shared among biased transistor wells during transition intervals when transitioning from one bias mode to another.

    Monitoring Circuit and Method
    38.
    发明申请
    Monitoring Circuit and Method 审中-公开

    公开(公告)号：US20180150120A1

    公开(公告)日：2018-05-31

    申请号：US15361405

    申请日：2016-11-26

    Applicant: ARM Limited

    Inventor： Parameshwarappa Anand Kumar Savanth ,  Bal S. Sandhu ,  James Edward Myers ,  Alexander Stewart Weddell ,  David Walter Flynn

    IPC: G06F1/28 ,  G01R19/165

    CPC classification number: G06F1/28 ,  G01R19/16576

    Abstract: Broadly speaking, embodiments of the present techniques provide a voltage monitoring circuit for low power minimum-energy sensor nodes. The circuit comprises sensing circuitry to sense a monitored signal having a plurality of operating signal states; a first comparator having a first input for receiving an upper threshold signal; and a second comparator having a first input for receiving a lower threshold signal, the upper and lower threshold signals defining a range which includes at least one signal state of the plurality of operating states of the monitored signal, wherein the first and second comparators have a bias input for receiving a bias configuration setting, the bias configuration setting being selectable according to an operating signal state of the monitored signal.

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