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    CONFIGURATION OF MULTI-DIE MODULES WITH THROUGH-SILICON VIAS
    31.
    发明申请
    CONFIGURATION OF MULTI-DIE MODULES WITH THROUGH-SILICON VIAS 审中-公开

    公开(公告)号：US20190332561A1

    公开(公告)日：2019-10-31

    申请号：US15964647

    申请日：2018-04-27

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Russell Schreiber ,  John Wuu ,  Michael K. Ciraula ,  Patrick J. Shyvers

    IPC: G06F13/38 ,  G06F13/42 ,  G06F13/40 ,  H01L25/065

    Abstract: A data processing system includes a processing unit that forms a base die and has a group of through-silicon vias (TSVs), and is connected to a memory system. The memory system includes a die stack that includes a first die and a second die. The first die has a first surface that includes a group of micro-bump landing pads and a group of TSV landing pads. The group of micro-bump landing pads are connected to the group of TSVs of the processing unit using a corresponding group of micro-bumps. The first die has a group of memory die TSVs. The subsequent die has a first surface that includes a group of micro-bump landing pads and a group of TSV landing pads connected to the group of TSVs of the first die. The first die communicates with the processing unit using first cycle timing, and with the subsequent die using second cycle timing.

    CANARY CIRCUIT WITH PASSGATE TRANSISTOR VARIATION
    33.
    发明申请
    CANARY CIRCUIT WITH PASSGATE TRANSISTOR VARIATION 有权
    具有PASSGATE TRANSISTOR变化的加速电路

    公开(公告)号：US20150029799A1

    公开(公告)日：2015-01-29

    申请号：US13949343

    申请日：2013-07-24

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Russell Schreiber

    IPC: G11C29/02

    CPC classification number: G11C29/021 ,  G11C8/08 ,  G11C11/418 ,  G11C29/025 ,  G11C29/028 ,  G11C2029/1202

    Abstract: A canary circuit with passgate transistor variation is described herein. The canary circuit includes a memory canary circuit that has a plurality of bitcells. Each bitcell has at least a passgate transistor that is driven by a wordline voltage. The canary circuit further includes a regulator circuit that outputs a wordline voltage that accounts for a predetermined offset of a threshold voltage of the passgate transistor. In an embodiment, the regulator circuit is a subtractor circuit that generates the wordline voltage from a reference voltage based in part on the threshold voltage variation of the passgate transistor.

    Abstract translation: 本文描述了具有通道晶体管变化的金丝雀电路。 金丝雀电路包括具有多个位单元的存储器金丝雀电路。 每个位单元至少具有由字线电压驱动的通道晶体管。 金丝雀电路还包括调节器电路，其输出考虑了通路晶体管的阈值电压的预定偏移的字线电压。 在一个实施例中，调节器电路是一个减法器电路，其部分地基于通道晶体管的阈值电压变化从参考电压产生字线电压。

    VOLTAGE-AWARE SIGNAL PATH SYNCHRONIZATION
    34.
    发明申请
    VOLTAGE-AWARE SIGNAL PATH SYNCHRONIZATION 有权
    电压识别信号路径同步

    公开(公告)号：US20140125381A1

    公开(公告)日：2014-05-08

    申请号：US13668705

    申请日：2012-11-05

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Russell Schreiber ,  John Wuu ,  Keith Kasprak

    IPC: H03K19/00 ,  G06F17/50

    CPC classification number: G06F17/50 ,  G06F13/1689 ,  G06F13/4291 ,  G06F17/5045 ,  G06F2217/62 ,  H03K19/00 ,  H05K3/00

    Abstract: An integrated circuit (IC) generates clock delay control signals based on its operational voltage level. The clock delay control signals are routed to corresponding clock gating logic that controls the synchronous capturing of the outputs of corresponding signal paths. The clock gating logic delays the clock signal used by the corresponding flip-flop in response to an assertion of the corresponding received clock delay control. Thus, the clock signal used to capture the outputs of certain signal paths may be delayed under certain voltage conditions. This selective clock path delay for different signal paths enables the IC to use a higher clock frequency, or more reliably latch the path outputs at a certain clock frequency, even though different signal paths may exhibit different relative path delays under different operating voltage conditions.

    Abstract translation: 集成电路（IC）根据其工作电压电平产生时钟延迟控制信号。 时钟延迟控制信号被路由到对应的时钟门控逻辑，其控制相应信号路径的输出的同步捕获。 响应于对应的接收时钟延迟控制的断言，时钟门控逻辑延迟由相应触发器使用的时钟信号。 因此，用于捕获某些信号路径的输出的时钟信号可能在某些电压条件下被延迟。 即使在不同的工作电压条件下不同的信号路径可能表现出不同的相对路径延迟，不同信号路径的这种选择性时钟路径延迟使得IC能够使用更高的时钟频率，或者更可靠地锁定一定时钟频率的路径输出。

    Dual read port latch array bitcell
    36.
    发明授权
    Dual read port latch array bitcell 有权

    公开(公告)号：US12073919B2

    公开(公告)日：2024-08-27

    申请号：US17359445

    申请日：2021-06-25

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Arijit Banerjee ,  John J. Wuu ,  Russell Schreiber

    IPC: G11C8/16 ,  G06F30/392 ,  G11C11/418 ,  G11C11/419

    CPC classification number: G11C8/16 ,  G06F30/392 ,  G11C11/418 ,  G11C11/419

    Abstract: An apparatus and method for providing efficient floor planning, power, and performance tradeoffs of memory accesses. A dual read port and single write port memory bit cell uses two asymmetrical read access circuits for conveying stored data on two read bit lines. The two read bit lines are pre-charged to different voltage reference levels. The layout of the memory bit cell places the two read bit lines on an opposed edge from the single write bit line. The layout uses a dummy gate placed over both p-type diffusion and n-type diffusion between the edges. The layout has a same number of p-type transistors as n-type transistors despite using asymmetrical read access circuits. The layout also has a contacted gate pitch that is one more than the number of p-type transistors.

    Split read port latch array bit cell
    37.
    发明授权
    Split read port latch array bit cell 有权

    公开(公告)号：US12033721B2

    公开(公告)日：2024-07-09

    申请号：US17359446

    申请日：2021-06-25

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Arijit Banerjee ,  John J. Wuu ,  Russell Schreiber

    IPC: G11C8/16 ,  G06F30/392 ,  G11C11/418 ,  G11C11/419

    CPC classification number: G11C8/16 ,  G06F30/392 ,  G11C11/418 ,  G11C11/419

    Abstract: An apparatus and method for providing efficient floor planning, power, and performance tradeoffs of memory accesses. Adjacent bit cells in a column of an array use a split read port such that the bit cells do not share a read bit line while sharing a write bit line. The adjacent bit cells include asymmetrical read access circuits that convey data stored by latch circuitry of a corresponding bit cell to a corresponding read bit line. The layout of adjacent bit cells provides a number of contacted gate pitches per bit cell that is less than a sum of the maximum number of metal gates in layout of each of the adjacent bit cells divided by the number of adjacent bit cells.

    Static Random Access Memory Read Path with Latch
    39.
    发明申请
    Static Random Access Memory Read Path with Latch 有权

    公开(公告)号：US20210158855A1

    公开(公告)日：2021-05-27

    申请号：US16692714

    申请日：2019-11-22

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Arijit Banerjee ,  Russell Schreiber ,  Kyle Whittle

    IPC: G11C11/4091 ,  G11C11/419 ,  G11C11/4074 ,  G11C7/10

    Abstract: A read path for reading data from a memory includes a sense amplifier having data (SAT) and data complement (SAC) output nodes and a latch. The latch includes an input tri-state inverter including first and second PMOS transistors connected between VDD and an intermediate node, and first and second NMOS transistors connected between VSS and the intermediate node. A gate connection of the first PMOS and NMOS transistors is connected to the SAT node; a gate connection of the second PMOS transistor is connected to a sense amplifier enable complement input; and a gate connection of the second NMOS transistor is connected to a sense amplifier enable input. The latch also includes an output driver with an input connected to the intermediate node and an output connected to a data output node. The latch thus has two gate delays between the SAT node and the data output node.

    TIMER FOR USE DUAL VOLTAGE SUPPLIES
    40.
    发明申请
    TIMER FOR USE DUAL VOLTAGE SUPPLIES 审中-公开

    公开(公告)号：US20200312389A1

    公开(公告)日：2020-10-01

    申请号：US16370579

    申请日：2019-03-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Srinivas R. Sathu ,  John Wuu ,  Russell Schreiber ,  Martin Piorkowski

    IPC: G11C7/22 ,  G11C11/419

    Abstract: A timing circuit includes an input for receiving the control signal from a logic circuit operating with a first supply voltage and an output for supplying a control signal to a circuit operating with a second supply voltage different from the first supply voltage. The timing circuit also includes a plurality of delay elements connected in series between the input and output and supplied with the first supply voltage, and one or more NFET footer transistors that couple respective delay elements to a negative supply rail, the NFET footer transistors having the second supply voltage applied to their gates. A memory apparatus employing such a circuit is provided.

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