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    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WITH TWIN-WELL
    31.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WITH TWIN-WELL 有权
    非易失性二极管半导体存储器件

    公开(公告)号：US20080283896A1

    公开(公告)日：2008-11-20

    申请号：US12175201

    申请日：2008-07-17

    申请人： Mitsuhiro Noguchi ,  Minori Kajimoto

    发明人： Mitsuhiro Noguchi ,  Minori Kajimoto

    IPC分类号： H01L29/00

    CPC分类号： H01L27/11546 ,  H01L27/105 ,  H01L27/11526

    摘要： A nonvolatile semiconductor memory device includes a first well of a first conductivity type, which is formed in a semiconductor substrate of the first conductivity type, a plurality of memory cell transistors that are formed in the first well, a second well of a second conductivity type, which includes a first part that surrounds a side region of the first well and a second part that surrounds a lower region of the first well, and electrically isolates the first well from the semiconductor substrate, and a third well of the second conductivity type, which is formed in the semiconductor substrate. The third well has a less depth than the second part of the second well.

    摘要翻译： 非易失性半导体存储器件包括形成在第一导电类型的半导体衬底中的第一导电类型的第一阱，形成在第一阱中的多个存储单元晶体管，第二导电类型的第二阱 ，其包括围绕第一阱的侧部区域的第一部分和围绕第一阱的下部区域的第二部分，并且将第一阱与半导体衬底以及第二导电类型的第三阱电隔离， 其形成在半导体衬底中。 第三井具有比第二井的第二部分更少的深度。

    Method for manufacturing a semiconductor device
    32.
    发明授权
    Method for manufacturing a semiconductor device 失效
    半导体器件的制造方法

    公开(公告)号：US07402495B2

    公开(公告)日：2008-07-22

    申请号：US11412951

    申请日：2006-04-28

    申请人： Minori Kajimoto ,  Mitsuhiro Noguchi

    发明人： Minori Kajimoto ,  Mitsuhiro Noguchi

    IPC分类号： H01L21/336 ,  H01L21/8236 ,  H01L21/8238

    CPC分类号： H01L27/105 ,  H01L21/76807 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/78

    摘要： A method of manufacturing a semiconductor device includes forming a first semiconductor region of a first conductive type and a second semiconductor region of a second conductive type in a predetermined region of the semiconductor substrate of a first conductive type; and first to third ion implantation processes sequentially executed for controlling threshold voltages corresponding to each transistor formed on the semiconductor substrate the first semiconductor region, and the second semiconductor region respectively. The first ion implantation process is executed in a high-threshold low-voltage transistor forming region of the first semiconductor region after forming the first semiconductor region. The second ion implantation process is executed in a high-threshold low-voltage transistor forming region of the second semiconductor region. The third ion implantation is executed simultaneously in the low-threshold low-voltage transistor forming regions of the semiconductor substrate and the second semiconductor region respectively.

    摘要翻译： 一种制造半导体器件的方法包括在第一导电类型的半导体衬底的预定区域中形成第一导电类型的第一半导体区域和第二导电类型的第二半导体区域; 以及分别顺序地执行用于控制对应于形成在半导体衬底上的每个晶体管的第一半导体区域和第二半导体区域的阈值电压的第一至第三离子注入工艺。 在形成第一半导体区域之后，第一离子注入工艺在第一半导体区域的高阈值低电压晶体管形成区域中执行。 在第二半导体区域的高阈值低压晶体管形成区域中执行第二离子注入工艺。 分别在半导体衬底和第二半导体区域的低阈值低压晶体管形成区域中同时执行第三离子注入。

    Semiconductor device and method for fabricating the same
    33.
    发明授权
    Semiconductor device and method for fabricating the same 失效
    半导体装置及其制造方法

    公开(公告)号：US07381641B2

    公开(公告)日：2008-06-03

    申请号：US11158074

    申请日：2005-06-22

    申请人： Ryuichi Kamo ,  Minori Kajimoto ,  Hiroaki Tsunoda ,  Yuuichiro Murahama

    发明人： Ryuichi Kamo ,  Minori Kajimoto ,  Hiroaki Tsunoda ,  Yuuichiro Murahama

    IPC分类号： H01L21/4763

    CPC分类号： H01L27/115 ,  H01L27/11521

    摘要： A semiconductor device such as a flash memory includes a semiconductor substrate, two gate insulating films formed on the substrate so as to have a first film thickness and a second film thickness smaller than the first film thickness respectively, and a polycrystalline silicon film formed on the gate insulating films so that parts of the polycrystalline silicon film on the respective gate insulating films are on a level with each other and serving as a gate electrode. The substrate is formed with a recess defined by a bottom and sidewalls substantially perpendicular to the bottom, the recess corresponding to the part of the gate insulating film with the first film thickness.

    摘要翻译： 诸如闪速存储器的半导体器件包括半导体衬底，在衬底上形成的第一膜厚度和第二膜厚度分别形成在第一膜厚度和第二膜厚度上的两个栅极绝缘膜，以及形成在第一膜厚度上的多晶硅膜 栅极绝缘膜，使得各个栅极绝缘膜上的多晶硅膜的一部分彼此成一层并且用作栅电极。 衬底形成有由底部限定的凹部和基本上垂直于底部的侧壁，凹部对应于具有第一膜厚度的栅极绝缘膜的部分。

    Nonvolatile semiconductor memory and method for fabricating the same
    34.
    发明申请
    Nonvolatile semiconductor memory and method for fabricating the same 失效
    非易失性半导体存储器及其制造方法

    公开(公告)号：US20080122098A1

    公开(公告)日：2008-05-29

    申请号：US12000396

    申请日：2007-12-12

    申请人： Minori Kajimoto ,  Mitsuhiro Noguchi ,  Akira Goda

    发明人： Minori Kajimoto ,  Mitsuhiro Noguchi ,  Akira Goda

    IPC分类号： H01L23/52 ,  H01L21/4763

    CPC分类号： H01L27/11568 ,  H01L21/76838 ,  H01L27/115 ,  H01L27/11521

    摘要： A nonvolatile semiconductor memory includes a first semiconductor layer; second semiconductor regions formed on the first semiconductor layer having device isolating regions extended in a column direction; a first interlayer insulator film formed above the first semiconductor layer; a lower conductive plug connected to the second semiconductor regions; a first interconnect extended in a row direction; a second interlayer insulator formed on the lower conductive plug and the first interlayer insulator film; an upper conductive plug; and a second interconnect formed on the second interlayer insulator contacting with the top of the upper conductive plug extended in the column direction.

    摘要翻译： 非易失性半导体存储器包括：第一半导体层; 形成在第一半导体层上的第二半导体区域，具有沿列方向延伸的器件隔离区域; 形成在所述第一半导体层上方的第一层间绝缘膜; 连接到第二半导体区域的下导电插塞; 沿行方向延伸的第一互连; 形成在下导电插塞和第一层间绝缘膜上的第二层间绝缘膜; 上导电插头; 以及形成在与沿列方向延伸的上导电插塞的顶部接触的第二层间绝缘体上的第二互连。

    Nonvolatile semiconductor memory
    35.
    发明授权
    Nonvolatile semiconductor memory 有权
    非易失性半导体存储器

    公开(公告)号：US07245534B2

    公开(公告)日：2007-07-17

    申请号：US11135415

    申请日：2005-05-24

    申请人： Akira Goda ,  Mitsuhiro Noguchi ,  Minori Kajimoto ,  Yuji Takeuchi

    发明人： Akira Goda ,  Mitsuhiro Noguchi ,  Minori Kajimoto ,  Yuji Takeuchi

    IPC分类号： G11C11/34

    CPC分类号： G11C8/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521

    摘要： A nonvolatile semiconductor memory includes: a memory cell array constituted by word lines, bit lines, and electrically erasable/rewritable memory cell transistors, which have respective tunnel insulating films and are arranged at the intersections of the word lines and the bit lines; and a word line transfer transistor, which is separated by an element isolation region, has a source diffusion layer, a channel region, a gate insulating film on the channel region, and a drain diffusion layer, and is connected to a word line and a gate electrode formed on the gate insulating film via a word line contact plug formed in the drain diffusion layer. The channel width of the word line transfer transistor is at least six times width of the word line contact plug, and the distance in a second direction between the word line contact plug and corresponding element isolation region is greater than distance in a first direction between the word line contact plug and corresponding element isolation region where, the first direction denotes a direction from the source diffusion layer towards the drain diffusion layer, and the second direction denotes a direction perpendicular to the first direction.

    摘要翻译： 非易失性半导体存储器包括：由字线，位线和电可擦除/可重写存储单元晶体管构成的存储单元阵列，其具有相应的隧道绝缘膜并且布置在字线和位线的交点处; 并且由元件隔离区隔开的字线传输晶体管在沟道区上具有源极扩散层，沟道区，栅极绝缘膜和漏极扩散层，并且连接到字线和 栅极通过形成在漏极扩散层中的字线接触插塞形成在栅极绝缘膜上。 字线传输晶体管的沟道宽度是字线接触插塞的至少六倍宽度，并且字线接触插塞和对应元件隔离区域之间的第二方向上的距离大于第二方向上的距离 字线接触插塞和对应元件隔离区域，其中第一方向表示从源极扩散层朝向漏极扩散层的方向，第二方向表示与第一方向垂直的方向。

    Nonvolatile semiconductor memory
    39.
    发明申请
    Nonvolatile semiconductor memory 失效
    非易失性半导体存储器

    公开(公告)号：US20050128843A1

    公开(公告)日：2005-06-16

    申请号：US10983617

    申请日：2004-11-09

    申请人： Minori Kajimoto ,  Mitsuhiro Noguchi ,  Hiroshi Maejima ,  Takahiko Hara

    发明人： Minori Kajimoto ,  Mitsuhiro Noguchi ,  Hiroshi Maejima ,  Takahiko Hara

    IPC分类号： H01L21/3205 ,  H01L21/8247 ,  H01L23/52 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157 ,  H01L29/7881 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A nonvolatile semiconductor memory according to the present invention includes memory cell units, which include data select lines formed in parallel to each other, data transfer lines crossing the data select lines and aligned in parallel to each other, and electrically rewritable memory cell transistors disposed at intersections of the data transfer lines and the data select lines. It further includes: a memory cell array block in which the memory cell units are disposed along the data select lines; first source lines, connected to one end of the memory cell units, and aligned along the data select lines; and second source lines electrically connected to the first source lines, and disposed along the data select lines.

    摘要翻译： 根据本发明的非易失性半导体存储器包括：存储单元单元，其包括彼此并联形成的数据选择线，与数据选择线相交并且彼此并联排列的数据传输线;以及电可重写存储单元晶体管， 数据传输线和数据选择线的交点。 它还包括：存储单元阵列块，其中存储单元单元沿数据选择线设置; 第一源极线，连接到存储单元单元的一端，并沿数据选择线对齐; 以及第二源极线，其电连接到第一源极线，并且沿着数据选择线布置。