公开(公告)号：US09934184B1

公开(公告)日：2018-04-03

申请号：US14865431

申请日：2015-09-25

Applicant: Amazon Technologies, Inc.

Inventor： Guy Nakibly ,  Adi Habusha ,  Nafea Bshara ,  Itai Avron

IPC: G06F13/00 ,  G06F3/00 ,  G06F13/40 ,  G06F13/364 ,  G06F13/42 ,  G06F13/16

CPC classification number: G06F13/4054 ,  G06F13/1626 ,  G06F13/364 ,  G06F13/4282

Abstract: Provided are systems and methods for distributing ordering tasks in a computing system that includes master and target devices. In some implementations, a computing device is provided. The computing device may include a master device that is operable to initiate transactions. The computing device may further include a target device that is operable to receive transactions. In some implementations, the master device may be configured to transmit one or more transactions to the target device. The master device may further asynchronously indicate to the target device a number of transactions to execute. The master device may further asynchronously receive from the target device a number of transactions executed. The master device may then signal that at least one transaction from the one or more transactions it sent has completed.

公开(公告)号：US20160098365A1

公开(公告)日：2016-04-07

申请号：US14872964

申请日：2015-10-01

Applicant: Amazon Technologies, Inc.

Inventor： Nafea Bshara ,  Adi Habusha ,  Guy Nakibly ,  Zorik Machulsky

IPC: G06F13/10 ,  G06F13/42 ,  G06F13/24

Abstract: Techniques for emulating a configuration space by a peripheral device may include receiving a configuration access request, determining that the configuration access request is for a configuration space other than a native configuration space of the peripheral device, and retrieving an emulated configuration from an emulated configuration space. The configuration access request can then be serviced by using the emulated configuration.

Abstract translation: 用于由外围设备模拟配置空间的技术可以包括接收配置访问请求，确定配置访问请求是用于除了外围设备的本机配置空间之外的配置空间，以及从仿真配置空间中检索仿真配置 。 然后可以使用仿真配置来对配置访问请求进行处理。

公开(公告)号：US20240126705A1

公开(公告)日：2024-04-18

申请号：US18538699

申请日：2023-12-13

Applicant: Amazon Technologies, Inc.

Inventor： Nafea Bshara ,  Adi Habusha ,  Guy Nakibly ,  Georgy Machulsky

IPC: G06F13/10 ,  G06F9/50 ,  G06F13/24 ,  G06F13/42

CPC classification number: G06F13/105 ,  G06F9/5077 ,  G06F13/24 ,  G06F13/4282 ,  G06F2213/0026 ,  G06F2213/0058

Abstract: Techniques for emulating a configuration space may include emulating a set of configuration registers in an integrated circuit device for a set of functions corresponding to a type of peripheral device. The type of peripheral device represented by the integrated circuit device can be modified by changing the set of configuration registers being emulated in the integrated circuit device. Multiple sets of configuration registers can also be emulated to support different virtual machines or different operating systems.

公开(公告)号：US11755496B1

公开(公告)日：2023-09-12

申请号：US17547888

申请日：2021-12-10

Applicant: Amazon Technologies, Inc.

Inventor： Peter Barry ,  Adi Habusha ,  Martin Pohlack

IPC: G06F12/1009 ,  G06F12/0882 ,  G06F12/06 ,  G06F12/02

CPC classification number: G06F12/1009 ,  G06F12/0238 ,  G06F12/0646 ,  G06F12/0882 ,  G06F2212/7201

Abstract: A computer system and methods are disclosed for mitigating side-channel attacks using memory aliasing. The computer system includes a memory, a memory controller and a cache. Responsive to determining to share a memory location among processes, the address of the memory may be aliased to another address within the same address space, with the address and aliased address assigned to respective ones of the processes. The memory controller manages the address space according to an aliasing region and a non-aliasing region, with addresses corresponding to the non-aliasing region being passed through to the memory. Addresses corresponding to the aliasing region are translated by the memory controller to match corresponding non-aliased memory addresses allowing aliased and non-aliased addresses to access same memory locations. A cache may cache accesses to memory addresses, including the non-aliased and aliased addresses, with different cache locations for selected according to the respective addresses of memory.

公开(公告)号：US11720444B1

公开(公告)日：2023-08-08

申请号：US17548190

申请日：2021-12-10

Applicant: Amazon Technologies, Inc.

Inventor： Ofer Naaman ,  Osnat Katz ,  Nir Bar-Or ,  Adi Habusha

IPC: G06F11/07 ,  G06F11/10 ,  G06F12/02 ,  G06F12/0891

CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F11/0772 ,  G06F12/0238 ,  G06F12/0891

Abstract: A system captures errors and stores an obsolete line bit qualifier per cache entry that can be used to dynamically mark a specific cache entry as obsolete. For example, the cache entry can be marked as obsolete after detecting repetitive single-bit errors on a same cache entry within a predetermined period of time. For cache lines marked as obsolete, a cache controller can ensure that the cache line entry remains unused. The detection of a repetitive single-bit error can be accomplished by implementing a counter per cache entry and a timer. The counter counts errors within a timer window, and a repetitive error is reported if the counter reaches a threshold level. By catching repetitive single-bit errors before such errors spread to multi-bit errors, the system can increase the life span of the server computer.

公开(公告)号：US11343176B2

公开(公告)日：2022-05-24

申请号：US16450837

申请日：2019-06-24

Applicant: Amazon Technologies, Inc.

Inventor： Sergey Kleyman ,  Adi Habusha ,  Lior Podorowski ,  Ofer Naaman

IPC: H04L12/00 ,  H04L45/302 ,  H04L45/745 ,  H04L47/24 ,  H04L67/568 ,  H04L49/20

Abstract: In various implementations, provided are systems and methods for an integrated circuit including a completer device, a requester device, and an interconnect fabric. The requester device is configured to generate transactions to the completer device, where each transaction includes a request packet that includes an attribute associated with the completer device; and the interconnect fabric is coupled to the requester device and the completer device. The integrated circuit can also include a QoS regulator configured to identify, based on a first attribute associated with the completer device, a first QoS value establishing a first priority level for a first request packet generated by the requester device, and modify the first request packet to include the first QoS value.

公开(公告)号：US11275690B1

公开(公告)日：2022-03-15

申请号：US16995091

申请日：2020-08-17

Applicant: Amazon Technologies, Inc.

Inventor： Michael Zuzovski ,  Ofer Naaman ,  Adi Habusha

IPC: G06F12/084 ,  G06F12/0871 ,  G06F9/54

Abstract: Techniques are disclosed for transferring a message between a sender agent and a receiver agent via a shared memory having a main memory and a cache. Feedback data indicative of a number of read messages in the shared memory is generated by the receiver agent. The feedback data is sent from the receiver agent to the sender agent. A number of unread messages in the shared memory is estimated by the sender agent based on the number of read messages. A threshold for implementing a caching policy is set by the sender agent based on the feedback data. The message is designated as cacheable if the number of unread messages is less than the threshold and as non-cacheable if the number of unread messages is greater than the threshold. The message is written to the shared memory based on the designation.

公开(公告)号：US11237981B1

公开(公告)日：2022-02-01

申请号：US16588206

申请日：2019-09-30

Applicant: Amazon Technologies, Inc.

Inventor： Adi Habusha ,  Ali Ghassan Saidi ,  Ohad Gdalyahu

IPC: G06F12/122 ,  G06F12/0831 ,  G06F9/455 ,  G06F13/28

Abstract: Methods and integrated circuit devices for accelerating memory page classification are provided. Memory systems typically have a combination of faster memory devices and slower memory devices. Frequently accessed memory pages (hot pages) should be maintained in the faster memory devices while less frequently accessed memory pages (cold pages) should be maintained in the slower memory devices. Classification of memory pages as hot or cold pages may be performed by an integrated circuit device that reads counter values that count transactions to corresponding memory pages. A distribution of counter values may be determined, and memory pages may be identified as hot or cold memory pages based on thresholds applied to the distribution.

公开(公告)号：US10977192B1

公开(公告)日：2021-04-13

申请号：US15094656

申请日：2016-04-08

Applicant: Amazon Technologies, Inc.

Inventor： Adi Habusha ,  Nafea Bshara

IPC: G06F12/1036 ,  G06F12/1009 ,  G06F12/10

Abstract: Disclosed herein is an apparatus configured to log transactions of a translation lookaside buffer (TLB) into a software-accessible buffer. The apparatus includes a memory management unit (MMU) configured to translate a logical memory address to a physical memory address for accessing a physical memory. The apparatus also includes a TLB configured to store a plurality of entries, where each entry includes a logical memory page address and an associated physical memory page address. The apparatus further includes a software-accessible buffer and a TLB event logging circuit configured to detect an event associated with an entry of the TLB and store information regarding the detected event in the software-accessible buffer.

公开(公告)号：US10740466B1

公开(公告)日：2020-08-11

申请号：US15280897

申请日：2016-09-29

Applicant: Amazon Technologies, Inc.

Inventor： Nafea Bshara ,  Matthew Shawn Wilson ,  Eric Jason Brandwine ,  Anthony Nicholas Liguori ,  Yaniv Shapira ,  Mark Bradley Davis ,  Adi Habusha

IPC: G06F15/177 ,  G06F21/57 ,  G06F9/4401 ,  G06F21/72 ,  H04L9/06

Abstract: Interfaces of a compute node on a printed circuit board can be secured by obfuscating the information communicated over the interfaces. Data to be communicated between the compute node and a device on the printed circuit board using an interface can be encrypted, and an address corresponding to the data to be communicated can be scrambled. In addition, the compute node can be the root of trust which can provide secure boot of different components using an on-chip mechanism, and without relying on external devices.