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31.发明授权Segmented dataline scheme in a memory with enhanced full fault coverage memory cell testability 有权具有增强的全故障覆盖存储器单元可测性的存储器中的分段数据线方案公开(公告)号：US07286382B1
公开(公告)日：2007-10-23
申请号：US11590333
申请日：2006-10-31
CPC分类号： G11C29/50 , G11C7/12 , G11C11/41 , G11C11/419 , G11C2029/1204
摘要： A memory includes a plurality of row segments, with each row segment having a number of memory cells coupled to a corresponding dataline segment pair. Dataline driver circuits are provided between row segments to buffer signals on adjacent dataline segments. A control circuit is coupled to at least one row segment, and provides control signals to the at least one row segment and to the dataline driver circuits.
摘要翻译： 存储器包括多个行段，其中每个行段具有耦合到对应的数据段段对的多个存储器单元。 数据线驱动器电路提供在行段之间以缓冲相邻数据段上的信号。 控制电路耦合到至少一个行段，并且向至少一个行段和数据线驱动器电路提供控制信号。
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32.发明授权Enzyme-catalyzed metal deposition for the enhanced in situ detection of immunohistochemical epitopes and nucleic acid sequences 有权酶催化的金属沉积用于增强免疫组织化学表位和核酸序列的原位检测公开(公告)号：US07632652B2
公开(公告)日：2009-12-15
申请号：US10877919
申请日：2004-06-24
IPC分类号： C12Q1/42 , C12Q1/44 , C12Q1/54 , C12Q1/68 , G01N33/53 , G01N33/543 , G01N33/567
CPC分类号： G01N33/581 , C07F9/093 , C07F9/65517 , C07F9/65522 , C07H15/20 , C07H15/24 , C07H15/26
摘要： The invention is directed to novel compositions of matter and methods of detecting in situ an immunohistochemical epitope or nucleic acid sequence of interest in a biological sample comprising binding an enzyme-labeled conjugate molecule to the epitope or sequence of interest in the presence of a redox-inactive reductive species and a soluble metal ion, thereby facilitating the reduction of the metal ion to a metal atom at or about the point where the enzyme is anchored. Novel phosphate derivatives of reducing agents are described that when exposed to a phosphatase are activated to their reducing form, thereby reducing metal ions to insoluble metal.
摘要翻译： 本发明涉及物质的新组合物和原位检测生物样品中感兴趣的免疫组织化学表位或核酸序列的方法，包括在氧化还原反应的存在下将酶标记的缀合物分子与感兴趣的表位或序列结合， 无活性还原物质和可溶性金属离子，从而有助于金属离子在酶被锚定的位置处或附近还原成金属原子。 描述了还原剂的新型磷酸酯衍生物，当暴露于磷酸酶被活化成其还原形式时，从而将金属离子还原成不溶性金属。
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公开(公告)号：US06981153B1
公开(公告)日：2005-12-27
申请号：US09724975
申请日：2000-11-28
CPC分类号： H04N21/23476 , G06F17/5054 , G06F21/76
摘要： It is sometimes desirable to protect a design used in a PLD from being copied. If the design is stored in a different device from the PLD and read into the PLD through a bitstream, the design may be encrypted as it is read into the PLD and decrypted within the PLD before being loaded into configuration memory cells for configuring the PLD. According to the invention, in such a device, a method is provided to prevent the design from being read back from the PLD in its decrypted state if it had been encrypted when loaded into the PLD.
摘要翻译： 有时期望保护PLD中使用的设计不被复制。 如果设计存储在与PLD不同的设备中并且通过比特流读入PLD，则在加载到用于配置PLD的配置存储器单元之前，设计可以在PLD中被读入PLD并被解密并被解密。 根据本发明，在这种设备中，提供了一种方法，用于防止在被加载到PLD中时将设计从PLD解密的状态下读回PLD。
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公开(公告)号：US06480954B2
公开(公告)日：2002-11-12
申请号：US09876745
申请日：2001-06-06
IPC分类号： G06F900
CPC分类号： H03K19/17776 , G06F17/5054 , H03K19/17752 , H03K19/17756 , H03K19/1776
摘要： A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration. The new configuration data may include off-chip or on-chip data. The present invention typically allocates at least one slice to user data memory and includes means for disabling access to at least one of the N memory cells.
摘要翻译： 可编程逻辑器件（PLD）包括至少一个可配置元件和用于配置可配置元件的多个可编程逻辑元件。 或者，PLD包括用于配置互连结构的互连结构和多个可编程逻辑元件。 在任一实施例中，至少一个可编程逻辑元件包括N个存储器单元。 N个存储器单元中的预定的一个形成存储器片的一部分，其中可编程逻辑器件的每个片的至少一部分被分配给配置数据或用户数据存储器。 通常，一个存储器片提供可编程逻辑器件的一个配置。 根据一个实施例，存储器访问端口耦合在N个存储器单元中的至少一个和任一个可配置元件或互连之间，从而有助于在一个配置期间将新的配置数据加载到其他存储器片段中。 新的配置数据可以包括片外或片上数据。 本发明通常将至少一个片分配给用户数据存储器，并且包括用于禁止对N个存储器单元中的至少一个的访问的装置。
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公开(公告)号：US5629637A
公开(公告)日：1997-05-13
申请号：US517017
申请日：1995-08-18
IPC分类号： H03K19/177
CPC分类号： H03K19/17752 , H03K19/17704 , H03K19/17756
摘要： A method of time multiplexing a programmable logic device (PLD) includes inputting a design for the PLD and dividing an evaluation of the logic of the design into a plurality of micro cycles. The method further includes identifying the logic not within a critical path of the design and rescheduling the identified logic for evaluation in other micro cycles. Alternatively, if the PLD includes a plurality of combinational logic elements, the method further includes scheduling a combinational logic element in a micro cycle no earlier than all the combinational logic elements that generate the input signals to said combinational logic element. Further alternatively, if the PLD includes a plurality of combinational logic elements and a plurality of sequential logic elements, the method further includes scheduling a sequential logic element in a micro cycle no earlier than all the combinational logic elements that generate input signals to the sequential logic element and scheduling each sequential logic element in a micro cycle no earlier than all the combinational logic elements or the sequential logic elements that the sequential logic element drives. If the PLD includes a plurality of combinational logic elements, a plurality of sequential logic elements, and a storage device, the method further includes mapping at least one of the sequential logic elements in the design into the storage device and scheduling the plurality of combinational logic elements and the remaining sequential logic elements.
摘要翻译： 一种时间复用可编程逻辑器件（PLD）的方法包括输入PLD的设计并将设计逻辑的评估分成多个微循环。 该方法还包括识别不在设计的关键路径内的逻辑，并重新安排所识别的逻辑以在其它微循环中进行评估。 或者，如果PLD包括多个组合逻辑元件，则该方法还包括在不早于生成到所述组合逻辑元件的输入信号的所有组合逻辑元件的微循环中调度组合逻辑元件。 此外，如果PLD包括多个组合逻辑元件和多个顺序逻辑元件，则该方法还包括在不早于生成到顺序逻辑的输入信号的所有组合逻辑元件的微循环中调度顺序逻辑元件 元素，并且在不超过所有组合逻辑元件或顺序逻辑元件驱动的顺序逻辑元件的微循环中调度每个顺序逻辑元件。 如果PLD包括多个组合逻辑元件，多个顺序逻辑元件和存储装置，则该方法还包括将设计中的顺序逻辑元件中的至少一个映射到存储装置中并调度多个组合逻辑 元素和剩余的顺序逻辑元素。
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公开(公告)号：US20100092534A1
公开(公告)日：2010-04-15
申请号：US12249576
申请日：2008-10-10
IPC分类号： A61F2/04 , A61K31/58 , A61K31/4355
CPC分类号： A61L31/10 , A61L31/16 , A61L2300/222 , A61L2300/416 , A61L2300/45
摘要： Described herein are implantable medical devices useful in treating vascular conditions such as restenosis. In one embodiment, stents are described in which a combination of bioactive agents is described for local delivery in the vasculature. The combination of bioactive agents comprises at least one compound capable of inhibiting smooth muscle cell proliferation and at least one compound capable of mitigating MCP- and/or TF induction. For example, a compound capable of inhibiting smooth muscle cell proliferation is a mTOR inhibitor and a compound capable of mitigating MCP-1 and/or TF induction is a corticosteroid.
摘要翻译： 本文描述了可用于治疗诸如再狭窄的血管病变的可植入医疗装置。 在一个实施方案中，描述了支架，其中描述了生物活性剂的组合用于脉管系统中的局部递送。 生物活性剂的组合包含至少一种能够抑制平滑肌细胞增殖的化合物和至少一种能够减轻MCP-和/或TF诱导的化合物。 例如，能够抑制平滑肌细胞增殖的化合物是mTOR抑制剂，能够缓解MCP-1和/或TF诱导的化合物是皮质类固醇。
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公开(公告)号：US07480690B2
公开(公告)日：2009-01-20
申请号：US11019854
申请日：2004-12-21
IPC分类号： G06F7/48
CPC分类号： G06F7/509
摘要： Described are arithmetic circuits divided logically into a product generator and an adder. Multiplexing circuitry logically disposed between the product generator and the adder supports conventional functionality by providing partial products from the product generator to addend terminals of the adder. The multiplexing circuitry can also be controlled to direct a number of external added inputs to the adder. The additional addend inputs can include inputs and outputs cascaded from other arithmetic circuits.
摘要翻译： 描述的是算术电路，逻辑上分为乘积发生器和加法器。 逻辑上位于产品发生器和加法器之间的多路复用电路通过提供来自产品发生器的部分乘积到加法器的末端来支持常规功能。 还可以控制复用电路以将多个外部添加的输入引导到加法器。 附加加数输入可以包括从其他算术电路级联的输入和输出。
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公开(公告)号：US07467177B2
公开(公告)日：2008-12-16
申请号：US11019853
申请日：2004-12-21
IPC分类号： G06F7/38
CPC分类号： G06F7/49963
摘要： Described are mathematical circuits that perform flexible rounding schemes. The circuits require few additional resources and can be adjusted dynamically to change the number of bits involved in the rounding. In one embodiment, a DSP circuit stores a rounding constant selected from the group of binary numbers 2(M−1) and 2(M−1)−1, calculates a correction factor, and sums the rounding constant, the correction factor, and a data item to obtain a rounded data item.
摘要翻译： 描述了执行灵活舍入方案的数学电路。 这些电路需要很少的额外资源，并且可以动态调整以改变舍入所涉及的位数。 在一个实施例中，DSP电路存储从二进制数2（M-1）和2（M-1）-1组中选择的舍入常数，计算校正因子，并将舍入常数，校正因子和 一个数据项以获得舍入的数据项。
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39.发明授权公开(公告)号：US07038519B1
公开(公告)日：2006-05-02
申请号：US10837324
申请日：2004-04-30
申请人： Raymond C. Pang , Jennifer Wong
发明人： Raymond C. Pang , Jennifer Wong
IPC分类号： H03H11/26
CPC分类号： H03K19/1738 , H03H11/26 , H03K2005/00195 , H03K2005/00228 , H03K2005/00234
摘要： A digital clock manager having differential clock signal paths is provided. The differential clock signal paths are provided by replacing single-ended circuit elements of a conventional digital clock manager with symmetrical cascade voltage switch logic (CVSL) circuit elements, including CVSL delay buffers, CVSL multiplexers, CVSL AND gates, CVSL OR gates and CVSL set-reset latches. These symmetrical CVSL AND gates, CVSL OR gates and CVSL set-reset latches represent new circuit elements.
摘要翻译： 提供具有差分时钟信号路径的数字时钟管理器。 差分时钟信号路径通过用传统数字时钟管理器的单端电路元件替代对称级联电压开关逻辑（CVSL）电路元件来提供，包括CVSL延迟缓冲器，CVSL多路复用器，CVSL与门，CVSL或门和CVSL组 - 锁存器。 这些对称的CVSL与门，CVSL或门和CVSL设置复位锁存器代表新的电路元件。
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40.发明授权Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks 有权在逻辑块阵列中提供紧密耦合的处理器和RAM块列的结构和方法公开(公告)号：US06803786B1
公开(公告)日：2004-10-12
申请号：US10386955
申请日：2003-03-11
申请人： Goran Bilski , Ralph D. Wittig , Jennifer Wong , David B. Squires
发明人： Goran Bilski , Ralph D. Wittig , Jennifer Wong , David B. Squires
IPC分类号： H03K19177
CPC分类号： H03K19/1776 , G06F15/7867 , H03K19/17732 , H03K19/17736 , H03K19/17796
摘要： Structures and methods of including processor capabilities in an existing PLD architecture with minimal disruption to the existing general interconnect structure. In a PLD including a column of block RAM (BRAM) blocks, the BRAM blocks are modified to create specialized logic blocks including a RAM, a processor, and a dedicated interface coupled between the RAM, the processor, and the general interconnect structure of the PLD. The additional area is obtained by increasing the width of the column of BRAM blocks. Because the interconnect structure remains virtually unchanged, the interconnections between the specialized logic blocks and the adjacent tiles are already in place, and the modifications do not affect the PLD routing software. In some embodiments, the processor can be optionally disabled, becoming transparent to the user. Other embodiments provide methods of modifying a PLD to include the structures and provide the capabilities described above.
摘要翻译： 在现有PLD架构中包含处理器能力的结构和方法，对现有的一般互连结构的影响最小。 在包括块RAM（BRAM）块列的PLD中，BRAM块被修改以创建专用的逻辑块，包括RAM，处理器和耦合在RAM，处理器和通用互连结构之间的专用接口 PLD。 通过增加BRAM块的列的宽度来获得附加区域。 因为互连结构几乎保持不变，所以专用逻辑块和相邻的瓦片之间的互连已经就位，并且修改不影响PLD路由软件。 在一些实施例中，处理器可以可选地被禁用，对于用户变得透明。 其他实施例提供了修改PLD以包括结构并提供上述能力的方法。
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