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公开(公告)号：US12002410B2
公开(公告)日：2024-06-04
申请号：US17642025
申请日：2021-04-08
Applicant: BOE Technology Group Co., Ltd.
Inventor： Hao Chen , Zhenyu Zhang , Jiao Zhao , Li Xiao , Dongni Liu , Haoliang Zheng , Liang Chen , Minghua Xuan , Ming Yang , Xinhong Lu , Qi Qi
CPC classification number: G09G3/32 , G01R31/52 , G01R31/54 , G09G3/006 , G09G3/035 , H01L25/0753 , H01L27/1244 , H01L33/62 , G09F9/33 , G09G2300/0426 , G09G2300/0452 , G09G2320/0233 , G09G2330/021
Abstract: An array substrate, a detection method for the array substrate, and a tiled display panel. In the array substrate, each of pixels (1) comprises sub-pixels (01) of at least three colors and a pixel driving chip (02) for driving each sub-pixel (01) to emit light; each sub-pixel (01) comprises at least one inorganic light-emitting diode; a display area (A1) further comprises: a positive signal line (Hm) connected to a positive electrode of each inorganic light-emitting diode, and a data signal line (Dm), a scanning line (Sn), and a reference signal line (Vm) connected to each pixel driving chip (02); each pixel driving chip (02) is used for writing signals of the data signal line (Dm) into the sub-pixels (01) of different colors under the control of the corresponding scanning line (Sn) in a time division manner.
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公开(公告)号：US11996017B2
公开(公告)日：2024-05-28
申请号：US17508866
申请日：2021-10-22
Applicant: BOE Technology Group Co., Ltd.
Inventor： Shuilang Dong , Xinhong Lu , Jingshang Zhou , Lei Zhao , Zhanfeng Cao , Dapeng Xue , Lizhong Wang , Guangcai Yuan
CPC classification number: G09F9/3026 , G09F9/33 , H01L33/62 , H10K77/111
Abstract: The present application discloses an array substrate and a splicing screen. The array substrate provided by an embodiment of the present application includes: a flexible base, wherein the flexible base includes a display region, a first region and a second region, the display region and at least one of the first region and the second region are located in different planes, and the first region is located between the display region and the second region; a plurality of signal lines, arranged on the display region and the first region; a plurality of fan-out lines, arranged on the second region and connected with the plurality of signal lines in a one-to-one correspondence; and a buffer cushion, arranged on the first region, wherein an orthographic projection of the buffer cushion on the flexible base does not overlap with orthographic projections of the signal lines on the flexible base.
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公开(公告)号：US20240154074A1
公开(公告)日：2024-05-09
申请号：US17775980
申请日：2021-06-22
Applicant: BOE Technology Group Co., Ltd.
Inventor： Xiaoyan Zhu , Jin Yang , Guangcai Yuan , Xinhong Lu , Ling Li
IPC: H01L33/54 , H01L25/075 , H01L33/62
CPC classification number: H01L33/54 , H01L25/0753 , H01L33/62 , H01L2933/005 , H01L2933/0066
Abstract: The present application provides a display panel, a method for fabricating a display panel and a displaying device. The display panel particularly includes at least two neighboring displaying base plates; each of the them includes a flexible substrate and a transparent cover plate that are provided in stack; the flexible substrate is delimited into a displaying region, a bending region and a bonding region, the displaying region and the bonding region are connected by the bending region, the displaying region and the bonding region are parallel, and the bonding region is located on one side of the displaying region that is away from the transparent cover plate; the transparent cover plate is provided with a light shielding layer on one side that is closer to the flexible substrate, and an orthographic projection of the bending region on the transparent cover plate is within an area of the light shielding layer.
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Patent Agency Ranking
公开(公告)号：US11728352B2
公开(公告)日：2023-08-15
申请号：US17354007
申请日：2021-06-22
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Xinhong Lu , Fangzhen Zhang , Guangcai Yuan , Zhanfeng Cao , Jiushi Wang , Ke Wang , Xiaoyan Zhu , Qi Qi , Jingshang Zhou , Zhaohui Qiang , Zhiwei Liang
CPC classification number: H01L27/124 , H01L25/167 , H01L27/1248 , H01L27/1259 , H01L27/1218
Abstract: The present disclosure provides a driving substrate including: a flexible substrate base, a plurality of thin film transistors on the flexible substrate base and a first conductive pattern layer on a side of the thin film transistors distal to the flexible substrate base. The first conductive pattern layer includes: a plurality of first connection terminals in the display region and a plurality of signal supply lines in the bendable region. A first number of first connection terminals are electrically coupled to first electrodes of the plurality of thin film transistors. The plurality of signal supply lines are coupled to a second number of first connection terminals other than the first number of first connection terminals. At least one inorganic insulating layer including a hollowed-out pattern in the bendable region is between the first conductive pattern layer and the flexible substrate base.
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公开(公告)号：US11532686B2
公开(公告)日：2022-12-20
申请号：US16330719
申请日：2018-09-11
Applicant: BOE Technology Group Co., Ltd.
Inventor： Xinhong Lu , Ke Wang , Hehe Hu , Ce Ning , Wei Yang
IPC: H01L29/78 , H01L27/32 , H01L29/786
Abstract: An array substrate includes a base substrate; a first thin film transistor on the base substrate and including a first active layer, a first gate electrode, a first source electrode and a first drain electrode; a second thin film transistor on the base substrate and including a second active layer, a second gate electrode, a second source electrode and a second drain electrode; a first gate insulating layer between the first active layer and the first gate electrode; and a second gate insulating layer between the second active layer and the second gate electrode, the second gate insulating layer being different from the first gate insulating layer. The first source electrode, the first drain electrode, and the second gate electrode are in a same layer. The first source electrode and the first drain electrode are on a side of the second gate insulating layer distal to the base substrate.
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公开(公告)号：US11362114B2
公开(公告)日：2022-06-14
申请号：US16765216
申请日：2019-12-06
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Wei Yang , Guangcai Yuan , Ce Ning , Xinhong Lu , Tianmin Zhou , Xin Yang
IPC: H01L27/12
Abstract: A method of manufacturing an array substrate includes: forming a first semiconductor pattern and a first insulating layer group sequentially on a base substrate; forming a second semiconductor pattern and a second insulating layer group sequentially on the first insulating layer group; forming two first via holes in the first insulating layer group and the second insulating layer group to expose the first semiconductor pattern, annealing the exposed first semiconductor pattern and then removing an oxide layer on a surface of the first semiconductor pattern; forming connecting wires in the first via holes; forming second via holes in the second insulating layer group to expose the second semiconductor pattern, and forming a first source electrode and a first drain electrode in the second via holes such that the first source electrode or the first drain electrode covers and is connected to one of the connecting wires.
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公开(公告)号：US11316003B2
公开(公告)日：2022-04-26
申请号：US16959010
申请日：2020-02-25
Applicant: BOE Technology Group Co., Ltd.
Inventor： Xue Dong , Guangcai Yuan , Haixu Li , Zhanfeng Cao , Ke Wang , Zhijun Lv , Fei Wang , Huijuan Wang , Zhiwei Liang , Xinhong Lu
IPC: H01L27/32
Abstract: Disclosed are an array substrate, and a display device, and a method for manufacturing the same. The array substrate includes: a base substrate, and a thin film transistor, a planarization pattern, a bonding pattern, and a conductive structure that are disposed on the base substrate. The thin film transistor, the planarization pattern, and the bonding pattern are laminated in a direction going distally from the base substrate. The planarization pattern is provided with a via and a groove, the conductive structure is disposed in the via, wherein the bonding pattern is conductive and is electrically connected to the thin film transistor by the conductive structure, an orthographic projection of the bonding pattern on the base substrate falls outside an orthographic projection of the groove on the base substrate, and the groove is configured to accommodate an adhesive.
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公开(公告)号：US20210359063A1
公开(公告)日：2021-11-18
申请号：US16330719
申请日：2018-09-11
Applicant: BOE Technology Group Co., Ltd.
Inventor： Xinhong Lu , Ke Wang , Hehe Hu , Ce Ning , Wei Yang
IPC: H01L27/32 , H01L29/786
Abstract: An array substrate includes a base substrate; a first thin film transistor on the base substrate and including a first active layer, a first gate electrode, a first source electrode and a first drain electrode; a second thin film transistor on the base substrate and including a second active layer, a second gate electrode, a second source electrode and a second drain electrode; a first gate insulating layer between the first active layer and the first gate electrode; and a second gate insulating layer between the second active layer and the second gate electrode, the second gate insulating layer being different from the first gate insulating layer. The first source electrode, the first drain electrode, and the second gate electrode are in a same layer. The first source electrode and the first drain electrode are on a side of the second gate insulating layer distal to the base substrate.
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