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公开(公告)号：US20160259190A1
公开(公告)日：2016-09-08
申请号：US14348359
申请日：2013-11-27
Inventor： Changjiang Yan , Jing Li , Tiansheng Li , Zhenyu Xie , Xu Chen
IPC: G02F1/1368 , G02F1/1362 , H01L27/12 , G02F1/1343
CPC classification number: G02F1/1368 , G02F1/13439 , G02F1/136209 , H01L27/1248 , H01L27/1259 , H01L29/78633
Abstract: The present invention discloses an array substrate and a manufacturing method thereof, and a display device, and relates to the field of display technology, in order to reduce the leakage current of the TFT, improve the stability of the TFT, and enhance the display effect of the display device. The array substrate comprises: a transparent substrate, a TFT on the transparent substrate, a first passivation layer covering the TFT, a first transparent electrode on a surface of the first passivation layer, and a light blocking structure for preventing light transmission provided at a position, corresponding to a channel of the TFT, on a side of the TFT away from the transparent substrate.
Abstract translation: 本发明公开了阵列基板及其制造方法以及显示装置，涉及显示技术领域，为了降低TFT的漏电流，提高TFT的稳定性，提高显示效果 的显示装置。 阵列基板包括：透明基板，透明基板上的TFT，覆盖TFT的第一钝化层，第一钝化层的表面上的第一透明电极，以及用于防止透光的遮光结构， 对应于TFT的沟道，在TFT的远离透明基板的一侧。
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32.发明授权Fabricating method of thin film transistor, thin film transistor and display panel 有权薄膜晶体管，薄膜晶体管和显示面板的制造方法公开(公告)号：US09324873B2
公开(公告)日：2016-04-26
申请号：US14421931
申请日：2014-04-25
Inventor： Jing Li , Zhenyu Xie , Xu Chen , Wenyu Zhang , Da Xu
IPC: H01L21/00 , H01L21/20 , H01L27/092 , H01L29/786 , H01L21/02 , H01L29/66 , H01L21/311
CPC classification number: H01L29/78675 , H01L21/0217 , H01L21/02532 , H01L21/02592 , H01L21/02672 , H01L21/31111 , H01L27/1281 , H01L29/66757 , H01L29/78603
Abstract: Embodiments of the invention provide a fabricating method a thin film transistor, a thin film transistor and a display panel, so as to improve carrier mobility in the polycrystalline silicon. The fabricating method a thin film transistor comprises following M1, depositing an inducing layer on a substrate; M2, etching a recess in the inducing layer by an etching process, the recess having an edge with a prescribed shape; M3, depositing an amorphous silicon layer in the recess having an edge with a prescribed shape, and inducing the amorphous silicon layer to form a polycrystalline silicon layer by crystallization method, polycrystalline silicon grains in the polycrystalline silicon layer arranging in a direction vertical to the edge of the recess by the limitation of the edge of the recess, and the polycrystalline silicone layer and the inducing layer together forming a semiconductor layer; and M4, forming a gate insulating layer, a gate, a passivation layer and a source and a drain connecting with the semiconductor layer sequentially on the semiconductor layer.
Abstract translation: 本发明的实施例提供薄膜晶体管，薄膜晶体管和显示面板的制造方法，以提高多晶硅中的载流子迁移率。 制造方法薄膜晶体管包括以下M1，在衬底上沉积诱导层; M2，通过蚀刻处理蚀刻诱导层中的凹部，凹部具有规定形状的边缘; M3，在具有规定形状的边缘的凹部中沉积非晶硅层，并且通过结晶法诱导非晶硅层形成多晶硅层，多晶硅层中的多晶硅晶粒沿垂直于边缘的方向排列 通过限制凹部的边缘，并且多晶硅层和诱导层一起形成半导体层; 和M4，在半导体层上依次形成栅极绝缘层，栅极，钝化层以及与半导体层连接的源极和漏极。
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公开(公告)号：US09261744B2
公开(公告)日：2016-02-16
申请号：US14439948
申请日：2014-08-26
Inventor： Tiansheng Li , Zhenyu Xie
IPC: H01L27/14 , G02F1/1345 , H01L29/423 , G02F1/1362 , G02F1/1368 , H01L21/308 , H01L21/311 , H01L21/3213 , H01L27/12
CPC classification number: G02F1/13454 , G02F1/1362 , G02F1/1368 , G02F2001/136231 , H01L21/308 , H01L21/31144 , H01L21/32139 , H01L27/1222 , H01L27/1248 , H01L27/1288 , H01L29/423
Abstract: The present invention discloses an array substrate, a fabricating method of thereof and a display device. The array substrate comprises a base substrate, and a pattern of a gate, a pattern of a gate insulating layer, a pattern of a pixel electrode, a pattern of an ohmic contact layer, a pattern of an active layer, and a pattern of source-drain electrodes formed on the base substrate. The pattern of the pixel electrode is positioned between the pattern of the gate insulating layer and the pattern of the ohmic contact layer. The technical solutions of the present disclosure can reduce one mask process, thus lowering fabrication cost and improving product yield.
Abstract translation: 本发明公开了阵列基板及其制造方法以及显示装置。 阵列基板包括基底基板，栅极图案，栅极绝缘层的图案，像素电极的图案，欧姆接触层的图案，有源层的图案和源的图案 在基底基板上形成电极。 像素电极的图案位于栅极绝缘层的图案和欧姆接触层的图案之间。 本公开的技术方案可以减少一个掩模过程，从而降低制造成本并提高产品产量。
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公开(公告)号：US09190438B2
公开(公告)日：2015-11-17
申请号：US14125830
申请日：2012-11-26
Inventor： Tiansheng Li , Shaoying Xu , Zhenyu Xie
IPC: H01L27/146
CPC classification number: H01L27/14612 , H01L27/14603 , H01L27/14632 , H01L27/1464 , H01L27/14658 , H01L27/14687 , H01L27/14689 , H01L27/14692
Abstract: A sensor and its fabrication method are provided. The sensor comprises: a base substrate, a group of gate lines and a group of data lines arranged as crossing each other, and a plurality of sensing elements arranged in an array and defined by the group of gate lines and the group of data lines, each sensing element comprising a Thin Film Transistor (TFT) device and a photodiode sensing device, wherein the photodiode sensor device comprises: a bias line disposed on the base substrate; a transparent electrode disposed on the bias line and being electrically contacted with the bias line; a photodiode disposed on the transparent electrode; and a receiving electrode disposed on the photodiode; the TFT device is located above the photodiode. When the sensor is functioning, light is directly transmitted onto the photodiode sensor device through the base substrate. In comparison with conventional technologies, the light loss is largely reduced and the light absorption usage ratio is improved.
Abstract translation: 提供传感器及其制造方法。 该传感器包括：基底基板，一组栅极线和一组布置为彼此交叉的数据线;以及多个感测元件，其排列成阵列并由栅极线组和数据线组限定， 每个感测元件包括薄膜晶体管（TFT）器件和光电二极管感测器件，其中所述光电二极管传感器器件包括：设置在所述基底衬底上的偏置线; 透明电极，设置在偏置线上并与偏置线电接触; 设置在所述透明电极上的光电二极管; 和设置在光电二极管上的接收电极; TFT器件位于光电二极管的上方。 当传感器工作时，光通过基底直接传输到光电二极管传感器装置上。 与常规技术相比，光损失大大降低，光吸收率比提高。
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35.发明授权公开(公告)号：US09171732B1
公开(公告)日：2015-10-27
申请号：US14514968
申请日：2014-10-15
Inventor： Tiansheng Li , Zhenyu Xie
IPC: H01L21/336 , H01L21/306 , H01L27/12 , H01L29/66
CPC classification number: H01L21/32137 , H01L21/32139 , H01L29/66765
Abstract: A method for manufacturing a thin film transistor according to the present disclosure may include the following steps of: performing a two-step etching on an active layer such that part of the active layer is consistent with a source-drain electrode layer, and etching the active layer within a photoresist-removed-area to form an active layer tail; ashing a photoresist layer such that a contour of the photoresist layer is consistent with that of the source-drain electrode layer; further etching the source-drain electrode layer to form a source-drain electrode layer pattern including a source electrode and a drain electrode, and etching off a doped semiconductor layer between the source electrode and the drain electrode, and meanwhile etching off the active layer tail.
Abstract translation: 根据本公开的制造薄膜晶体管的方法可以包括以下步骤：在有源层上执行两步蚀刻，使得有源层的一部分与源极 - 漏极电极层一致，并蚀刻 在光致抗蚀剂去除区域内的活性层以形成活性层尾部; 灰化光致抗蚀剂层，使得光致抗蚀剂层的轮廓与源极 - 漏极电极层的轮廓一致; 进一步蚀刻源极 - 漏极电极层以形成包括源电极和漏电极的源 - 漏电极层图案，并且蚀刻源电极和漏电极之间的掺杂半导体层，同时蚀刻有源层尾 。
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Patent Agency Ranking
公开(公告)号：US20150194461A1
公开(公告)日：2015-07-09
申请号：US14123992
申请日：2012-11-16
Inventor： Tiansheng Li , Xiaohui Jiang , Shaoying Xu , Zhenyu Xie
IPC: H01L27/146
CPC classification number: H01L27/14687 , H01L27/14612 , H01L27/14643 , H01L27/14658 , H01L27/14689 , H01L27/14692
Abstract: A method for fabricating a sensor, comprising: forming a pattern of a bias line on a base substrate by using a first patterning process; forming a pattern of a transparent electrode, a pattern of a photodiode, a pattern of a receive electrode, a pattern of a source electrode, a pattern of a drain electrode, a pattern of a data line and a pattern of an ohmic layer by using a second patterning process; forming a pattern of an active layer, a pattern of a first passivation layer, a pattern of a gate electrode and a pattern of a gate line by using a third patterning process. The above method reduces the number of used mask in the fabrication processes as well as the production cost and simplifies the production process, thereby significantly improves the production capacity and the yield rate.
Abstract translation: 一种用于制造传感器的方法，包括：通过使用第一图案化工艺在基底基板上形成偏置线图案; 通过使用透明电极的图案，光电二极管的图案，接收电极的图案，源极的图案，漏极的图案，数据线的图案和欧姆层的图案 第二图案化过程; 通过使用第三图案化工艺形成有源层的图案，第一钝化层的图案，栅电极的图案和栅极线的图案。 上述方法减少了制造工艺中使用的掩模的数量以及生产成本，并简化了生产过程，从而显着提高了生产能力和产量。
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公开(公告)号：US09041111B2
公开(公告)日：2015-05-26
申请号：US14107068
申请日：2013-12-16
Inventor： Zhenyu Xie
IPC: H01L23/62 , H01L27/146
CPC classification number: H01L27/14689 , H01L27/1259 , H01L27/14612 , H01L27/14636 , H01L27/14658 , H01L27/14692
Abstract: A flat panel detector includes a photoelectric conversion layer and a pixel detecting element disposed under the photoelectric conversion layer. The pixel detecting element includes: a pixel electrode for receiving charges, a storage capacitor for storing the received charges, and a thin film transistor for controlling outputting of the stored charges. The storage capacitor includes a first electrode and a second electrode. The first electrode includes an upper electrode and a bottom electrode that are disposed opposite to each other and electrically connected. A second electrode is sandwiched between the upper electrode and the bottom electrode. It is insulated between the upper electrode and the second electrode and between the second electrode and the bottom electrode.
Abstract translation: 平板检测器包括光电转换层和设置在光电转换层下面的像素检测元件。 像素检测元件包括：用于接收电荷的像素电极，用于存储接收的电荷的存储电容器，以及用于控制所存储的电荷的输出的薄膜晶体管。 存储电容器包括第一电极和第二电极。 第一电极包括彼此相对设置并电连接的上电极和底电极。 第二电极夹在上电极和底电极之间。 它在上电极和第二电极之间以及在第二电极和底电极之间被绝缘。
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公开(公告)号：US08900909B2
公开(公告)日：2014-12-02
申请号：US13704769
申请日：2012-11-08
Inventor： Shaoying Xu , Zhenyu Xie , Xu Chen
IPC: H01L21/00 , H01L27/146 , H01L31/18
CPC classification number: H01L31/18 , H01L27/14658 , H01L27/14692
Abstract: An embodiment of the invention discloses a manufacture method of a sensor comprising: preparing gate scanning lines on a substrate; depositing a gate insulating layer on the gate scanning lines; sequentially depositing a gate insulation thin film, an active layer thin film, an ohmic contact layer thin film, a first conducting layer thin film and a photoelectric conversion layer thin film, and after the depositing, processing a lamination structure of the thin films with a gray-tone mask plate to obtain switch devices and photoelectric sensing devices; and then sequentially preparing a first passivation layer, bias lines and a second passivation layer.
Abstract translation: 本发明的实施例公开了一种传感器的制造方法，包括：在基板上准备栅极扫描线; 在栅极扫描线上沉积栅极绝缘层; 依次沉积栅极绝缘薄膜，有源层薄膜，欧姆接触层薄膜，第一导电层薄膜和光电转换层薄膜，并且在沉积之后，将薄膜的层叠结构用 灰色蒙版板获得开关器件和光电传感器件; 然后顺序地制备第一钝化层，偏置线和第二钝化层。
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公开(公告)号：US20140063503A1
公开(公告)日：2014-03-06
申请号：US13984342
申请日：2013-03-12
Inventor： Tiansheng Li , Changjiang Yan , Shaoying Xu , Zhenyu Xie , Xiaohui Jiang
CPC classification number: H01L22/10 , G01N21/59 , H01L21/67253 , H01L22/12 , H01L22/26 , H01L2924/0002 , H01L2924/00
Abstract: An etching time detection means and an etching time detection method for an etching device. The detection means comprises: a light wave emitter fixed on one substrate of the etching device, a light wave receiver fixed on another substrate and opposed to the light wave emitter, a detection system communicated with the light wave emitter and the light wave receiver for receiving light intensity signals and calculating etching time. With the detection means and the detection method, the automatical detection of etching time can be achieved and the deviation caused by visual observation can be effectively avoided.
Abstract translation: 用于蚀刻装置的蚀刻时间检测装置和蚀刻时间检测方法。 检测装置包括：固定在蚀刻装置的一个基板上的光波发射器，固定在另一基板上并与光波发射器相对的光波接收器，与光波发射器通信的检测系统和用于接收的光波接收器 光强信号和计算蚀刻时间。 利用检测装置和检测方法，可以实现蚀刻时间的自动检测，并且可以有效地避免由视觉观察引起的偏差。
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公开(公告)号：US11623216B2
公开(公告)日：2023-04-11
申请号：US16318116
申请日：2018-05-17
Inventor： Tiansheng Li , Zhenyu Xie , Lijun Mao
IPC: B01L3/00 , G01N33/52 , H01L23/538 , H01L23/31 , C12M1/34
Abstract: A sample testing apparatus for characterizing at least one target molecule in a testing sample includes a substrate and at least one detection device over the substrate. Each detection device includes a plurality of electrodes, a plurality of data lines, and a probe. Each electrode is configured, upon reaction of the probe with one of the at least one target molecule, to sense an electrical signal, and then to transmit the electrical signal via the one data line. Each data line includes a first film layer and at least one other film layer disposed over the first film layer. The first film layer can be at a substantially same layer, and have a first composition substantially same, as the electrodes. One or more of the at least one other film layer can have a composition having a relatively lower electric resistance than the first composition.
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