公开(公告)号：US20060089820A1

公开(公告)日：2006-04-27

申请号：US10973186

申请日：2004-10-25

Applicant: Bin Yu ,  Yong Rui

Inventor： Bin Yu ,  Yong Rui

IPC: G06F11/30 ,  G21C17/00 ,  G06F15/00

CPC classification number: G06Q10/10

Abstract: An event-based system and process for recording and playback of collaborative electronic presentations is presented. The present system and process includes a technique for recording collaborative electronic presentations by capturing and storing the interactions between each participant and presentation data where each interaction event is timestamped and linked to a data file comprising the presentation data. The present system and process also includes a technique for playing back the recorded collaborative electronic presentation, which involves displaying the presentation data in an order it was originally presented and reproducing the recorded interactions between each participant and the displayed presentation data at the same point in the presentation that they were originally performed, based on the aforementioned timestamps.

公开(公告)号：US07019363B1

公开(公告)日：2006-03-28

申请号：US09476961

申请日：2000-01-03

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L29/76 ,  H01L29/94

CPC classification number: H01L29/7835 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/6659 ,  H01L29/66659

Abstract: A method of fabricating an integrated circuit utilizes symmetric source/drain junctions. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETS). The drain extension is deeper than the source extension. The source extension is more conductive than the drain extension. The transistor has reduced short channel effects and strong drive current and yet is reliable.

Abstract translation: 一种制造集成电路的方法采用对称的源极/漏极结。 该过程可用于P沟道或N沟道金属氧化物半导体效应晶体管（MOSFET）。 漏极扩展比源扩展更深。 源极延伸比漏极延伸更为导电。 晶体管减少了短沟道效应和强大的驱动电流，而且可靠。

公开(公告)号：US06998301B1

公开(公告)日：2006-02-14

申请号：US10653225

申请日：2003-09-03

Applicant: Bin Yu ,  Shibly S. Ahmed

Inventor： Bin Yu ,  Shibly S. Ahmed

IPC: H01L21/00 ,  H01L21/84

CPC classification number: H01L21/02672 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/2022 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for forming a tri-gate semiconductor device that includes a substrate and a dielectric layer formed on the substrate includes depositing a first dielectric layer on the dielectric layer and etching the first dielectric layer to form a structure. The method further includes depositing a second dielectric layer over the structure, depositing an amorphous silicon layer over the second dielectric layer, etching the amorphous silicon layer to form amorphous silicon spacers, where the amorphous silicon spacers are disposed on opposite sides of the structure, depositing a metal layer on at least an upper surface of each of the amorphous silicon spacers, annealing the metal layer to convert the amorphous silicon spacers to crystalline silicon fin structures, removing a portion of the second dielectric layer, depositing a gate material, and etching the gate material to form three gates.

Abstract translation: 一种形成三栅极半导体器件的方法，包括在衬底上形成的衬底和电介质层，包括在电介质层上沉积第一介电层并蚀刻第一介电层以形成结构。 该方法还包括在结构上沉积第二介电层，在第二介电层上沉积非晶硅层，蚀刻非晶硅层以形成非晶硅间隔物，其中非晶硅间隔物设置在结构的相对侧上，沉积 在每个非晶硅间隔物的至少上表面上的金属层，退火金属层以将非晶硅间隔物转化为晶体硅鳍结构，去除第二电介质层的一部分，沉积栅极材料，并蚀刻 门材料形成三门。

公开(公告)号：US06963104B2

公开(公告)日：2005-11-08

申请号：US10459576

申请日：2003-06-12

Applicant: Yider Wu ,  Bin Yu

Inventor： Yider Wu ,  Bin Yu

IPC: H01L21/336 ,  H01L21/8246 ,  H01L27/115 ,  H01L27/12 ,  H01L29/786 ,  H01L29/792 ,  H01L29/788

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/792

Abstract: A non-volatile memory device includes a substrate, an insulating layer, a fin, a number of dielectric layers and a control gate. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. The dielectric layers are formed over the fin and the control gate is formed over the dielectric layers. The dielectric layers may include oxide-nitride-oxide layers that function as a charge storage structure for the memory device.

Abstract translation: 非易失性存储器件包括衬底，绝缘层，鳍片，多个电介质层和控制栅极。 绝缘层形成在基板上，并且鳍形成在绝缘层上。 电介质层形成在鳍片之上，并且控制栅极形成在电介质层上。 电介质层可以包括用作存储器件的电荷存储结构的氧化物 - 氮化物 - 氧化物层。

公开(公告)号：US06958512B1

公开(公告)日：2005-10-25

申请号：US10770010

申请日：2004-02-03

Applicant: Yider Wu ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Yider Wu ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/786 ,  H01L29/788

CPC classification number: H01L29/42324 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7881

Abstract: A non-volatile memory device includes a substrate, an insulating layer, a fin, a conductive structure and a control gate. The insulating layer may be formed on the substrate and the fin may be formed on the insulating layer. The conductive structure may be formed near a side of the fin and the control gate may be formed over the fin. The conductive structure may act as a floating gate electrode for the non-volatile memory device.

Abstract translation: 非易失性存储器件包括衬底，绝缘层，鳍，导电结构和控制栅。 绝缘层可以形成在基板上，并且鳍可以形成在绝缘层上。 导电结构可以形成在鳍的一侧附近，并且控制栅可以形成在翅片上。 导电结构可以用作非易失性存储器件的浮栅电极。

公开(公告)号：US06933558B2

公开(公告)日：2005-08-23

申请号：US10726508

申请日：2003-12-04

Applicant: Wiley Eugene Hill ,  Haihong Wang ,  Yider Wu ,  Bin Yu

Inventor： Wiley Eugene Hill ,  Haihong Wang ,  Yider Wu ,  Bin Yu

IPC: G11C16/04 ,  H01L21/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/792

CPC classification number: H01L21/28273 ,  H01L27/115 ,  H01L27/11556 ,  H01L29/785

Abstract: A memory device includes a conductive structure, a number of dielectric layers and a control gate. The dielectric layers are formed around the conductive structure and the control gate is formed over the dielectric layers. A portion of the conductive structure functions as a drain region for the memory device and at least one of the dielectric layers functions as a charge storage structure for the memory device. The dielectric layers may include oxide-nitride-oxide layers.

Abstract translation: 存储器件包括导电结构，多个电介质层和控制栅极。 电介质层形成在导电结构周围，并且控制栅极形成在电介质层上。 导电结构的一部分用作存储器件的漏极区，并且至少一个介电层用作存储器件的电荷存储结构。 电介质层可以包括氧化物 - 氮化物 - 氧化物层。

公开(公告)号：US06921704B1

公开(公告)日：2005-07-26

申请号：US10700557

申请日：2003-11-05

Applicant: David Wu ,  Akif Sultan ,  Bin Yu

Inventor： David Wu ,  Akif Sultan ,  Bin Yu

IPC: H01L21/762 ,  H01L21/764 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/76

CPC classification number: H01L21/764 ,  H01L21/76224 ,  H01L21/823481 ,  H01L21/823878

Abstract: A method of forming a silicon-on-insulator semiconductor device including providing a substrate and forming a trench in the substrate, wherein the trench includes opposing side walls extending upwardly from a base of the trench. The method also includes depositing at least two insulating layers into the trench to form a shallow trench isolation structure, wherein an innermost of the insulating layers substantially conforms to the base and the two side walls of the trench and an outermost of the insulating layers spans the side walls of the trench so that a gap is formed between the insulating layers in the trench. The gap creates compressive forces within the shallow trench isolation structure, which in turn creates tensile stress within the surrounding substrate to enhance mobility of the device.

Abstract translation: 一种形成绝缘体上半导体器件的方法，包括提供衬底并在衬底中形成沟槽，其中沟槽包括从沟槽的基底向上延伸的相对的侧壁。 该方法还包括将至少两个绝缘层沉积到沟槽中以形成浅沟槽隔离结构，其中绝缘层的最内层基本上与基底一致并且沟槽的两个侧壁和绝缘层的最外层横跨 沟槽的侧壁，使得在沟槽中的绝缘层之间形成间隙。 间隙在浅沟槽隔离结构内产生压缩力，这反过来在周围的衬底内产生拉伸应力，以增强器件的移动性。

公开(公告)号：US06897527B2

公开(公告)日：2005-05-24

申请号：US10833112

申请日：2004-04-28

Applicant: Srikanteswara Dakshina-Murthy ,  Judy Xilin An ,  Zoran Krivokapic ,  Haihong Wang ,  Bin Yu

Inventor： Srikanteswara Dakshina-Murthy ,  Judy Xilin An ,  Zoran Krivokapic ,  Haihong Wang ,  Bin Yu

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/49 ,  H01L29/786 ,  H01L27/01

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/78654 ,  H01L29/78687

Abstract: A semiconductor device includes a fin and a layer formed on at least a portion of the fin. The fin includes a first crystalline material. The layer includes a second crystalline material, where the first crystalline material has a larger lattice constant than the second crystalline material to induce tensile strain within the layer.

Abstract translation: 半导体器件包括翅片和形成在鳍片的至少一部分上的层。 翅片包括第一结晶材料。 该层包括第二结晶材料，其中第一结晶材料具有比第二结晶材料更大的晶格常数以在层内引起拉伸应变。

公开(公告)号：US06893930B1

公开(公告)日：2005-05-17

申请号：US10161452

申请日：2002-05-31

Applicant: Bin Yu ,  Haihong Wang

Inventor： Bin Yu ,  Haihong Wang

IPC: H01L21/265 ,  H01L21/336

CPC classification number: H01L29/66598 ,  H01L21/26513 ,  H01L29/665 ,  H01L29/6653

Abstract: For fabricating a field effect transistor on an active device area of a semiconductor substrate, a gate dielectric and a gate electrode are formed on the active device area of the semiconductor substrate. Antimony (Sb) dopant is implanted into exposed regions of the active device area of the semiconductor substrate to form at least one of drain and source extension junctions and/or drain and source contact junctions. A low temperature thermal anneal process at a temperature less than about 950° Celsius is performed for activating the antimony (Sb) dopant within the drain and source extension junctions and/or drain and source contact junctions. In one embodiment of the present invention, the drain and source contact junctions are formed and thermally annealed before the formation of the drain and source extension junctions in a disposable spacer process for further minimizing heating of the drain and source extension junctions. In another embodiment of the present invention, the drain and source extension junctions and/or the drain and source contact junctions are formed to be amorphous before the thermal anneal process. In that case, a SPE (solid phase epitaxy) activation process in performed for activating the antimony (Sb) dopant within the amorphous drain and source extension junctions and/or the amorphous drain and source contact junctions at a temperature less than about 650° Celsius.

Abstract translation: 为了在半导体衬底的有源器件区域上制造场效应晶体管，在半导体衬底的有源器件区域上形成栅极电介质和栅电极。 将锑（Sb）掺杂剂注入到半导体衬底的有源器件区域的暴露区域中，以形成漏极和源极延伸结和/或漏极和源极接触结中的至少一个。 在低于约950℃的温度下进行低温热退火工艺，以激活漏极和源极延伸结和/或漏极和源极接触接点内的锑（Sb）掺杂剂。 在本发明的一个实施例中，在一次性间隔器工艺中形成漏极和源极延伸接头之前，形成漏极和源极接触接头并进行热退火，以进一步最小化漏极和源极延伸接点的加热。 在本发明的另一实施例中，在热退火工艺之前，将漏极和源极延伸接头和/或漏极和源极接触接点形成为非晶体。 在这种情况下，在低于约650℃的温度下，在非晶漏极和源极延伸结和/或非晶漏极和源极接触点内激活用于激活锑（Sb）掺杂剂的SPE（固相外延）激活过程 。

公开(公告)号：US06872647B1

公开(公告)日：2005-03-29

申请号：US10429780

申请日：2003-05-06

Applicant: Bin Yu ,  Judy Xilin An ,  Cyrus E. Tabery

Inventor： Bin Yu ,  Judy Xilin An ,  Cyrus E. Tabery

IPC: H01L21/033 ,  H01L21/336 ,  H01L29/06 ,  H01L29/786 ,  H01L21/3205 ,  H01L21/20 ,  H01L21/311

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L21/0337 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming multiple fins in a semiconductor device includes forming a structure having an upper surface and side surfaces on the semiconductor device. The semiconductor device includes a conductive layer located below the structure. The method also includes forming spacers adjacent the structure and selectively etching the spacers and the conductive layer to form the fins. The fins may be used in a FinFET device.

Abstract translation: 在半导体器件中形成多个散热片的方法包括形成具有半导体器件上表面和侧表面的结构。 半导体器件包括位于结构下方的导电层。 该方法还包括在该结构附近形成间隔物并选择性地蚀刻间隔物和导电层以形成翅片。 翅片可用于FinFET器件。