公开(公告)号：US06225661B1

公开(公告)日：2001-05-01

申请号：US09145786

申请日：1998-09-02

Applicant: Judy Xilin An ,  Bin Yu ,  Ming-Ren Lin

Inventor： Judy Xilin An ,  Bin Yu ,  Ming-Ren Lin

IPC: H01L27088

CPC classification number: H01L21/28194 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L2924/0002 ,  Y10S257/90 ,  Y10S438/981 ,  H01L2924/00

Abstract: A field effect transistor (FET) is formed on a silicon substrate, with a nitride gate insulator layer being deposited on the substrate and an oxide gate insulator layer being deposited on the nitride layer to insulate a gate electrode from source and drain regions in the substrate. The gate material is then removed to establish a gate void, and spacers are deposited on the sides of the void such that only a portion of the oxide layer is covered by the spacers. Then, the unshielded portion of the oxide layer is removed, thus establishing a step between the oxide and nitride layers that overlays the source and drain extensions under the gate void to reduce subsequent capacitive coupling and charge carrier tunneling between the gate and the extensions. The spacers are removed and the gate void is refilled with gate electrode material.

Abstract translation: 在硅衬底上形成场效应晶体管（FET），其中氮化物栅极绝缘体层沉积在衬底上，并且氧化物栅极绝缘体层沉积在氮化物层上以使栅电极与衬底中的源极和漏极区域绝缘 。 然后去除栅极材料以建立栅极空隙，并且间隔物沉积在空隙的侧面上，使得只有一部分氧化物层被间隔物覆盖。 然后，去除氧化物层的非屏蔽部分，从而在栅极空隙下的源极和漏极延伸层之间建立氧化物层和氮化物层之间的步骤，以减少栅极和延伸部之间的后续电容耦合和电荷载流子隧道。 去除间隔物，并用栅电极材料重新填充栅极空隙。

公开(公告)号：US6107667A

公开(公告)日：2000-08-22

申请号：US151146

申请日：1998-09-10

Applicant: Judy Xilin An ,  Bin Yu ,  Yowjuang W. Liu

Inventor： Judy Xilin An ,  Bin Yu ,  Yowjuang W. Liu

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/51 ,  H01L29/76 ,  H01L27/088 ,  H01L27/095 ,  H01L29/94 ,  H01L31/062

CPC classification number: H01L21/28194 ,  H01L21/28123 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/6659 ,  Y10S257/90

Abstract: A method for making a ULSI MOSFET includes establishing a void in a field oxide layer on a silicon substrate and filling the center of the void with a gate electrode. A high-k gate insulator is sandwiched between the gate electrode and the substrate. Around the void, a low-k gate spacer is formed, with the gate spacer being disposed directly above the source and drain extensions of the MOSFET.

Abstract translation: 制造ULSI MOSFET的方法包括在硅衬底上的场氧化物层中建立空隙并用栅电极填充空隙的中心。 高k栅极绝缘体夹在栅电极和衬底之间。 围绕空隙，形成低k栅极间隔物，栅极间隔物直接设置在MOSFET的源极和漏极延伸部分的上方。

公开(公告)号：US08222680B2

公开(公告)日：2012-07-17

申请号：US10274961

申请日：2002-10-22

Applicant: Ming-Ren Lin ,  Judy Xilin An ,  Zoran Krivokapic ,  Cyrus E. Tabery ,  Haihong Wang ,  Bin Yu

Inventor： Ming-Ren Lin ,  Judy Xilin An ,  Zoran Krivokapic ,  Cyrus E. Tabery ,  Haihong Wang ,  Bin Yu

IPC: H01L29/72

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/66818

Abstract: A double gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin, a first gate and a second gate. The first gate is formed on top of the fin. The second gate surrounds the fin and the first gate. In another implementation, a triple gate MOSFET includes a fin, a first gate, a second gate, and a third gate. The first gate is formed on top of the fin. The second gate is formed adjacent the fin. The third gate is formed adjacent the fin and opposite the second gate.

Abstract translation: 双栅极金属氧化物半导体场效应晶体管（MOSFET）包括鳍状物，第一栅极和第二栅极。 第一个门形成在鳍的顶部。 第二个门围绕翅片和第一个门。 在另一实施方案中，三栅极MOSFET包括鳍片，第一栅极，第二栅极和第三栅极。 第一个门形成在鳍的顶部。 第二个门形成在翅片附近。 第三栅极形成在翅片附近并与第二栅极相对。

公开(公告)号：US07781810B1

公开(公告)日：2010-08-24

申请号：US11538217

申请日：2006-10-03

Applicant: Judy Xilin An ,  Zoran Krivokapic ,  Haihong Wang ,  Bin Yu

Inventor： Judy Xilin An ,  Zoran Krivokapic ,  Haihong Wang ,  Bin Yu

IPC: H01L29/72

CPC classification number: H01L29/7855 ,  H01L21/823821 ,  H01L29/42384 ,  H01L29/7843 ,  H01L29/78684

Abstract: A device includes a fin, a first gate and a second gate. The first gate is formed adjacent a first side of the fin and includes a first layer of material having a first thickness and having an upper surface that is substantially co-planar with an upper surface of the fin. The second gate is formed adjacent a second side of the fin opposite the first side and includes a second layer of material having a second thickness and having an upper surface that is substantially co-planar with the upper surface of the fin, where the first thickness and the second thickness are substantially equal to a height of the fin.

Abstract translation: 一种装置包括鳍片，第一栅极和第二栅极。 第一门形成在鳍片的第一侧附近，并且包括具有第一厚度并且具有与鳍片的上表面基本共面的上表面的第一材料层。 所述第二浇口邻近所述翅片的与所述第一侧相对的第二侧形成，并且包括具有第二厚度并具有与所述翅片的上表面基本共面的上表面的第二材料层，其中所述第一厚度 并且第二厚度基本上等于翅片的高度。

公开(公告)号：US06833588B2

公开(公告)日：2004-12-21

申请号：US10274867

申请日：2002-10-22

Applicant: Bin Yu ,  Shibly S. Ahmed ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Zoran Krivokapic ,  Haihong Wang

Inventor： Bin Yu ,  Shibly S. Ahmed ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Zoran Krivokapic ,  Haihong Wang

IPC: H01L2701

CPC classification number: H01L29/785 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/66803

Abstract: A double-gate semiconductor device includes a substrate, an insulating layer, a fin and a gate. The insulating layer is formed on the substrate and the gate is formed on the insulating layer. The fin has a number of side surfaces, a top surface and a bottom surface. The bottom surface and at least a portion of the side surfaces of the fin are surrounded by the gate. The gate material surrounding the fin has a U-shaped cross-section at a channel region of the semiconductor device.

公开(公告)号：US06800885B1

公开(公告)日：2004-10-05

申请号：US10385652

申请日：2003-03-12

Applicant: Judy Xilin An ,  Bin Yu

Inventor： Judy Xilin An ,  Bin Yu

IPC: H01L2980

CPC classification number: H01L29/785 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/7856

Abstract: An asymmetric double gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a first fin formed on a substrate; a second fin formed on the substrate; a first gate formed adjacent first sides of the first and second fins, the first gate being doped with a first type of impurity; and a second gate formed between second sides of the first and second fins, the second gate being doped with a second type of impurity. An asymmetric all-around gate MOSFET includes multiple fins; a first gate structure doped with a first type of impurity and formed adjacent a first side of one of the fins; a second gate structure doped with the first type of impurity and formed adjacent a first side of another one of the fins; a third gate structure doped with a second type of impurity and formed between two of the fins; and a fourth gate structure formed at least partially beneath one or more of the fins.

Abstract translation: 非对称双栅极金属氧化物半导体场效应晶体管（MOSFET）包括在基板上形成的第一鳍片; 在所述基板上形成的第二翅片; 形成在所述第一和第二鳍片的第一侧附近的第一栅极，所述第一栅极掺杂有第一类型的杂质; 以及形成在所述第一和第二鳍片的第二侧之间的第二栅极，所述第二栅极掺杂有第二类型的杂质。 非对称全栅极MOSFET包括多个鳍片; 掺杂有第一类型杂质的第一栅极结构，并且邻近其中一个鳍片的第一侧形成; 掺杂有第一类型杂质的第二栅极结构，并且与另一个鳍片的第一侧相邻地形成; 掺杂有第二类杂质并形成在两个鳍之间的第三栅极结构; 以及至少部分地在一个或多个翅片下方形成的第四门结构。

公开(公告)号：US06706614B1

公开(公告)日：2004-03-16

申请号：US10145953

申请日：2002-05-15

Applicant: Judy Xilin An ,  Bin Yu

Inventor： Judy Xilin An ,  Bin Yu

IPC: H01L2176

CPC classification number: H01L29/66742 ,  H01L29/78618 ,  H01L29/78684

Abstract: A silicon-on-insulator(SOI) transistor. The SOI transistor having a source and a drain having a body disposed therebetween, the source being implanted with germanium to form an area of silicon-germanium adjacent a source/body junction in a lower portion of the source, the area of silicon-germanium in the source forming a hereto junction along a lower portion of the source/body junction.

Abstract translation: 绝缘体上硅（SOI）晶体管。 具有源极和漏极的SOI晶体管具有设置在其间的主体，源被注入锗以形成邻近源极的下部的源极/主体结的硅 - 锗的区域，硅 - 锗的面积 源沿着源/体结的下部形成本结。

公开(公告)号：US06706571B1

公开(公告)日：2004-03-16

申请号：US10274951

申请日：2002-10-22

Applicant: Bin Yu ,  Judy Xilin An ,  Cyrus E. Tabery ,  Haihong Wang

Inventor： Bin Yu ,  Judy Xilin An ,  Cyrus E. Tabery ,  Haihong Wang

IPC: H01L2100

CPC classification number: H01L29/785 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/78684

Abstract: A method of forming multiple structures in a semiconductor device includes depositing a film over a conductive layer, etching a trench in a portion of the film and forming adjacent the sidewalls of the trench. The film may then be etched, followed by an of the conductive layer to form the structures.

Abstract translation: 在半导体器件中形成多个结构的方法包括在导电层上沉积膜，蚀刻膜的一部分中的沟槽并且形成在沟槽的侧壁附近。 然后可以对该膜进行蚀刻，然后进行导电层的形成以形成结构。

公开(公告)号：US06448114B1

公开(公告)日：2002-09-10

申请号：US10128831

申请日：2002-04-23

Applicant: Judy Xilin An ,  Bin Yu ,  William G. En

Inventor： Judy Xilin An ,  Bin Yu ,  William G. En

IPC: H01L218234

CPC classification number: H01L27/1203 ,  H01L21/84

Abstract: A method of fabricating a silicon-on-insulator (SOI) chip having an active layer with a non-uniform thickness. The method includes the steps of providing a substrate; providing a buried oxide layer (BOX) on the substrate; providing an active layer on the BOX layer, the active layer having an initially uniform thickness; dividing the active layer into at least a first and a second tile; and altering the thickness of the active layer in the area of the second tile. The method also includes forming a plurality of partially depleted semiconductor devices from the active layer in the area of a thicker of the first and the second tiles and forming a plurality of fully depleted semiconductor devices from the active layer in the area of a thinner of the first and the second tiles.

Abstract translation: 一种制造具有不均匀厚度的有源层的绝缘体上硅（SOI）芯片的方法。 该方法包括提供基板的步骤; 在衬底上提供掩埋氧化物层（BOX）; 在BOX层上提供有源层，活性层具有最初均匀的厚度; 将活性层分成至少第一和第二瓦片; 并且改变第二瓦片区域中活性层的厚度。 该方法还包括在第一和第二瓦片较厚的区域中从有源层形成多个部分耗尽的半导体器件，并且在较薄的区域中从有源层形成多个完全耗尽的半导体器件 第一和第二个瓷砖。

公开(公告)号：US06414355B1

公开(公告)日：2002-07-02

申请号：US09770708

申请日：2001-01-26

Applicant: Judy Xilin An ,  Bin Yu ,  William G. En

Inventor： Judy Xilin An ,  Bin Yu ,  William G. En

IPC: H01L2701

CPC classification number: H01L27/1203 ,  H01L21/84

Abstract: A silicon-on-insulator (SOI) chip. The SOI chip has a substrate; a buried oxide (BOX) layer disposed on the substrate; and an active layer disposed on the BOX layer, the active layer divided into a first and a second tile, the first tile having a first thickness and the second tile having a second thickness, the second thickness being smaller than the first thickness. Also disclosed is a method of fabricating a silicon-on-insulator (SOI) chip having an active layer with a non-uniform thickness. The method includes the steps of providing a substrate; providing a buried oxide layer (BOX) on the substrate; providing an active layer on the BOX layer, the active layer having an initially uniform thickness; dividing the active layer into at least a first and a second tile; and altering the thickness of the active layer in the area of the second tile.

Abstract translation: 绝缘体上硅（SOI）芯片。 SOI芯片具有基板; 设置在基板上的掩埋氧化物（BOX）层; 以及设置在所述BOX层上的有源层，所述有源层被分为第一和第二瓦片，所述第一瓦片具有第一厚度，所述第二瓦片具有第二厚度，所述第二厚度小于所述第一厚度。 还公开了一种制造具有不均匀厚度的有源层的绝缘体上硅（SOI）芯片的方法。 该方法包括提供基板的步骤; 在衬底上提供掩埋氧化物层（BOX）; 在BOX层上提供有源层，活性层具有最初均匀的厚度; 将活性层分成至少第一和第二瓦片; 并且改变第二瓦片区域中活性层的厚度。