公开(公告)号：US20060253663A1

公开(公告)日：2006-11-09

申请号：US11124002

申请日：2005-05-06

申请人： James Johnson ,  Troy Manning

发明人： James Johnson ,  Troy Manning

IPC分类号： G06F13/00

CPC分类号： G11C7/1039 ,  G11C7/1048 ,  G11C11/401 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50012 ,  G11C2207/105 ,  G11C2207/2254

摘要： A synchronous dynamic random access memory (“SDRAM”) device includes a pipelined write data path coupling data from a data bus to a DRAM array, and a pipelined read data path coupling read data from the array to the data bus. The SDRAM device also includes a bypass path allowing the write data in the write data path to be coupled directly to the read data path without first being stored in the DRAM array. The write data are preferably coupled through the write data path by issuing a write command to the DRAM device, and the read data are preferably coupled through the read data path by issuing a read command to the DRAM device. The memory array is inhibited from responding to these commands so that the write data are not stored in the array, and read data from the array are not coupled to the read data path.

摘要翻译： 同步动态随机存取存储器（“SDRAM”）器件包括将从数据总线到DRAM阵列的数据耦合的流水线写入数据路径，以及将读取数据从阵列耦合到数据总线的流水线读取数据路径。 SDRAM器件还包括允许写入数据路径中的写入数据直接耦合到读取数据路径而不首先存储在DRAM阵列中的旁路路径。 写数据优选地通过向DRAM设备发出写命令而通过写数据路径耦合，并且读数据优选地通过向DRAM设备发出读命令通过读数据路径耦合。 禁止存储器阵列响应这些命令，使得写入数据不存储在阵列中，并且从阵列读取数据不耦合到读取数据路径。

公开(公告)号：US20050036367A1

公开(公告)日：2005-02-17

申请号：US10946772

申请日：2004-09-22

申请人： Todd Merritt ,  Troy Manning

发明人： Todd Merritt ,  Troy Manning

IPC分类号： G06F12/06 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  G11C11/34

CPC分类号： G11C7/109 ,  G06F12/0638 ,  G06F2212/2022 ,  G11C7/1021 ,  G11C7/1024 ,  G11C7/1027 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/22 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/4096

摘要： An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating toggling Read/Write control line at cycle frequency. Control line transition terminates access and initializes another burst access. Write cycle times are maximized thereby allowing increases in burst mode operating frequencies. Logic near sense amplifiers control write-data drivers thereby providing maximum write times without crossing current during I/O line equilibration. By gating global write-enable signals with global equilibrate signals locally at sense amps, local write-cycle control signals are provided and valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory. For nonburst mode, write begins following end of equilibration cycle to provide maximum write time without interfering with subsequent access-cycle address setup time.

摘要翻译： 地址选通锁存第一个地址。 突发周期会在内部增加地址选通信号。 只有在每次突发访问开始时才需要新的内存地址。 读/写命令每次突发存取发出一次，消除了循环频率下的切换读/写控制线。 控制线转换终止访问并初始化另一个突发访问。 写周期时间最大化，从而允许突发模式工作频率的增加。 读出放大器附近的逻辑控制写入数据驱动器，从而在I / O线平衡期间提供最大的写入时间，而无需交叉电流。 通过在感测放大器上本地使用全局平衡信号选通全局写使能信号，提供本地写周期控制信号，并且基本上在整个周期时间内减去突发存取存储器中的I / O线平衡周期。 对于非突发模式，写入开始于平衡周期结束后提供最大写入时间，而不会影响随后的访问周期地址建立时间。

公开(公告)号：US06472905B1

公开(公告)日：2002-10-29

申请号：US09691415

申请日：2000-10-17

申请人： Troy Manning

发明人： Troy Manning

IPC分类号： H03K190175

CPC分类号： H03K19/00361

摘要： A translator includes an initial circuit device configured to charge a translator output to a first voltage level in response to a change in an input signal. The translator further includes a sensing device configured to detect the output's potential approaching the first voltage level and smoothly shift charging functions over to a secondary circuit device, which will continue to charge the output up to a second voltage level.

公开(公告)号：US06255886B1

公开(公告)日：2001-07-03

申请号：US09560378

申请日：2000-04-28

申请人： Troy Manning

发明人： Troy Manning

IPC分类号： H03K508

CPC分类号： G05F3/24 ,  G05F3/242 ,  H02M3/073

摘要： A multi-phase charge pump continuously pumps to establish a DC voltage outside the range of supply and reference voltages. The multi-phase charge pump in one embodiment includes four stages operating in a ring with a four-phase clock. Each stage includes a three-mode charge pump that generates and provides reset and control signals to other stages. Each stage includes a pass transistor having a gate driven in excess of the DC voltage for efficient transfer of charge. The gate drive signal from a first stage is coupled to a next stage in the ring where it is used to generate the next gate drive signal. Each gate drive signal corresponds to one waveform having a phase skewed in time so that each stage in the ring is operating in a different mode. In a method of use, a first stepped voltage is developed on a first capacitor and selectively coupled to a second capacitor to develop a second stepped voltage of greater absolute value. The second stepped voltage gates charge transfer from a first stage and enables the selective coupling in a next stage in a sequence of pump stages. The pump stages include protection circuits protecting high-voltage nodes during burn-in testing. The charge pump includes a burn-in detector circuit for detecting burn-in conditions and for turning on the protection circuits and a pump regulator for regulating the output of the charge pump.

摘要翻译： 多相电荷泵连续泵浦以建立在供电和参考电压范围之外的直流电压。 在一个实施例中的多相电荷泵包括四个工作在具有四相时钟的环中的级。 每个级包括三模式电荷泵，其产生并向其他级提供复位和控制信号。 每个级包括具有驱动超过直流电压的栅极的传输晶体管，以有效地传送电荷。 来自第一级的栅极驱动信号被耦合到环中的下一级，其中它用于产生下一个栅极驱动信号。 每个栅极驱动信号对应于具有在时间上偏斜的相位的一个波形，使得环中的每个级都以不同的模式操作。 在使用方法中，在第一电容器上形成第一阶梯电压，并选择性地耦合到第二电容器以形成更大绝对值的第二阶梯电压。 第二阶梯式电压栅极从第一级电荷转移，并使得能够在一级泵阶段中进行下一级的选择性耦合。 泵级包括在老化测试期间保护高压节点的保护电路。 电荷泵包括用于检测老化条件并打开保护电路的老化检测器电路和用于调节电荷泵输出的泵调节器。

公开(公告)号：US6043558A

公开(公告)日：2000-03-28

申请号：US928875

申请日：1997-09-12

申请人： Troy Manning

发明人： Troy Manning

IPC分类号： H01L23/495 ,  H01L23/498 ,  H01L23/50 ,  H05K1/14 ,  H05K7/20 ,  H01L23/28 ,  H01L23/48

CPC分类号： H01L24/06 ,  H01L23/4951 ,  H01L23/49805 ,  H01L23/50 ,  H01L24/49 ,  H05K1/145 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/4826 ,  H01L2224/49 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/3011

摘要： A packaging technique for high speed components, such as high speed DRAMS, may involve a package which includes two opposed edges, one edge adapted to receive a power supply and ground contacts which may be ganged together to form a ganged power supply lead and a ganged ground lead. A second edge is arranged to receive normal signal contacts. In this way, the lead inductance may be minimized and the operation efficiency of the package may be improved.

摘要翻译： 用于诸如高速DRAMS的高速组件的封装技术可以涉及包括两个相对的边缘的封装，一个边缘适于接收电源和接地触点，所述边缘可以组合在一起以形成联合的电源引线和组合 地面线。 第二边缘被布置成接收正常的信号触点。 以这种方式，引线电感可以最小化，并且可以提高封装的操作效率。

公开(公告)号：US5831931A

公开(公告)日：1998-11-03

申请号：US890418

申请日：1997-07-09

申请人： Troy Manning

发明人： Troy Manning

IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  G11C8/00

CPC分类号： G11C11/407 ,  G11C7/1024 ,  G11C7/22

摘要： An integrated memory circuit is described which can be operated in a burst access mode. The memory circuit includes an address counter which changes column addresses in one of a number of predetermined patterns. The memory includes generator circuit for generating an internal control signal based upon external column address signals. The generator circuit detects the first active transition of the column address signals and the first inactive transition of the column address signals.

摘要翻译： 描述了可以以突发接入模式操作的集成存储器电路。 存储器电路包括地址计数器，其以多个预定模式之一改变列地址。 存储器包括用于基于外部列地址信号产生内部控制信号的发生器电路。 发生器电路检测列地址信号的第一有效转换和列地址信号的第一无效转换。

公开(公告)号：US5682354A

公开(公告)日：1997-10-28

申请号：US553986

申请日：1995-11-06

申请人： Troy Manning

发明人： Troy Manning

IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  G11C8/00

CPC分类号： G11C11/407 ,  G11C7/1024 ,  G11C7/22

摘要： An integrated memory circuit is described which can be operated in a burst access mode. The memory circuit includes an address counter which changes column addresses in one of a number of predetermined patterns. The memory includes generator circuit for generating an internal control signal based upon external column address signals. The generator circuit detects the first active transition of the column address signals and the first inactive transition of the column address signals.

摘要翻译： 描述了可以以突发接入模式操作的集成存储器电路。 存储器电路包括地址计数器，其以多个预定模式之一改变列地址。 存储器包括用于基于外部列地址信号产生内部控制信号的发生器电路。 发生器电路检测列地址信号的第一有效转换和列地址信号的第一无效转换。

公开(公告)号：US5642073A

公开(公告)日：1997-06-24

申请号：US418143

申请日：1995-04-05

申请人： Troy Manning

发明人： Troy Manning

IPC分类号： G05F3/24 ,  H02M3/07 ,  H03K5/08 ,  G05F3/02

CPC分类号： G05F3/24 ,  G05F3/242 ,  H02M3/073

摘要： A multi-phase charge pump continuously pumps to establish a DC voltage outside the range of supply and reference voltages. The multi-phase charge pump in one embodiment includes four stages operating in a ring with a four-phase clock. Each stage includes a three-mode charge pump that generates and provides reset and control signals to other stages. Each stage includes a pass transistor having a gate driven in excess of the DC voltage for efficient transfer of charge. The gate drive signal from a first stage is coupled to a next stage in the ring where it is used to generate the next gate drive signal. Each gate drive signal corresponds to one waveform having a phase skewed in time so that each stage in the ring is operating in a different mode. In a method of use, a first stepped voltage is developed on a first capacitor and selectively coupled to a second capacitor to develop a second stepped voltage of greater absolute value. The second stepped voltage gates charge transfer from a first stage and enables the selective coupling in a next stage in a sequence of pump stages. The pump stages include protection circuits protecting high-voltage nodes during burn-in testing. The charge pump includes a burn-in detector circuit for detecting burn-in conditions and for turning on the protection circuits and a pump regulator for regulating the output of the charge pump.

摘要翻译： 多相电荷泵连续泵浦以建立在供电和参考电压范围之外的直流电压。 在一个实施例中的多相电荷泵包括四个工作在具有四相时钟的环中的级。 每个级包括三模式电荷泵，其产生并向其他级提供复位和控制信号。 每个级包括具有驱动超过直流电压的栅极的传输晶体管，以有效地传送电荷。 来自第一级的栅极驱动信号被耦合到环中的下一级，其中它用于产生下一个栅极驱动信号。 每个栅极驱动信号对应于具有在时间上偏斜的相位的一个波形，使得环中的每个级都以不同的模式工作。 在使用方法中，在第一电容器上形成第一阶梯电压，并选择性地耦合到第二电容器以形成更大绝对值的第二阶梯电压。 第二阶梯式电压栅极从第一级电荷转移，并使得能够在一级泵阶段中进行下一级的选择性耦合。 泵级包括在老化测试期间保护高压节点的保护电路。 电荷泵包括用于检测老化条件并打开保护电路的老化检测器电路和用于调节电荷泵输出的泵调节器。

公开(公告)号：US08327224B2

公开(公告)日：2012-12-04

申请号：US12424766

申请日：2009-04-16

申请人： Troy Larsen ,  Martin Culley ,  Troy Manning

发明人： Troy Larsen ,  Martin Culley ,  Troy Manning

IPC分类号： H03M13/00

CPC分类号： G06F11/073 ,  G06F11/108 ,  G11C29/10

摘要： Methods for data recovery and memory systems are provided. According to at least one such method, when defective data is read from a memory location, the data is recovered by an XOR operation on the remaining good data and associated RAID data to reconstruct the defective data. The defective data is excluded from the XOR operation.

摘要翻译： 提供数据恢复和存储系统的方法。 根据至少一种这样的方法，当从存储器位置读取有缺陷的数据时，通过对剩余的良好数据和相关联的RAID数据进行异或运算来恢复数据以重建缺陷数据。 缺陷数据从异或运算中排除。

公开(公告)号：US20100095084A1

公开(公告)日：2010-04-15

申请号：US12250043

申请日：2008-10-13

申请人： Troy Manning

发明人： Troy Manning

IPC分类号： G06F12/10

CPC分类号： G06F12/0246 ,  G06F12/0292 ,  G06F2212/1044 ,  G06F2212/1048 ,  G06F2212/2022 ,  G06F2212/7201 ,  G06F2212/7208 ,  G11C16/102 ,  Y02D10/13

摘要： Solid state storage devices and methods for flash translation layers are disclosed. In one such translation layer, a sector indication is translated to a memory location by a parallel unit look-up table is populated by memory device enumeration at initialization. Each table entry is comprised of communication channel, chip enable, logical unit, and plane for each operating memory device found. When the sector indication is received, a modulo function operates on entries of the look-up table in order to determine the memory location associated with the sector indication.

摘要翻译： 公开了用于闪存转换层的固态存储设备和方法。 在一个这样的翻译层中，通过并行单元查找表将扇区指示转换为存储器位置，由初始化时的存储器设备枚举填充。 每个表条目由发现的每个操作存储器件的通信信道，芯片使能，逻辑单元和平面组成。 当接收到扇区指示时，模函数对查找表的条目进行操作，以便确定与扇区指示相关联的存储器位置。