公开(公告)号：US20150097220A1

公开(公告)日：2015-04-09

申请号：US14069174

申请日：2013-10-31

Applicant: BROADCOM CORPORATION

Inventor： Shom Surendran PONOTH ,  Changyok Park ,  Akira Ito

IPC: H01L27/06

CPC classification number: H01L27/0629

Abstract: A fin-shaped field-effect transistor device is provided. The fin-shaped field effect transistor device may include a semiconductor substrate having a top and a bottom surface. The fin-shaped field effect transistor device may also include a fin structure disposed on the top surface of the semiconductor substrate, where the fin structure includes a first sidewall and a second sidewall opposite of the first sidewall. The first sidewall is adjacent to a first region of the top surface of the semiconductor substrate and the second sidewall is adjacent to a second region of the top surface of the semiconductor substrate. The fin-shaped field effect transistor device may also include an insulation layer disposed above the fin structure and the first and second regions of the top surface. The fin-shaped field effect transistor device may also include a conductor structure disposed above and adjacent to the insulation layer.

Abstract translation: 提供了一种鳍状场效应晶体管器件。 鳍状场效应晶体管器件可以包括具有顶表面和底表面的半导体衬底。 鳍状场效应晶体管器件还可以包括设置在半导体衬底的顶表面上的翅片结构，其中鳍结构包括第一侧壁和与第一侧壁相对的第二侧壁。 第一侧壁与半导体衬底的顶表面的第一区相邻，第二侧壁与半导体衬底的顶表面的第二区相邻。 鳍状场效应晶体管器件还可以包括设置在鳍结构上方的绝缘层和顶表面的第一和第二区域。 鳍状场效应晶体管器件还可以包括设置在绝缘层上方并与绝缘层相邻的导体结构。

公开(公告)号：US20140299964A1

公开(公告)日：2014-10-09

申请号：US14246579

申请日：2014-04-07

Applicant: Broadcom Corporation

Inventor： Henry Kuo-Shun CHEN ,  Guang-Jye Shiau ,  Akira Ito

IPC: H01L49/02

CPC classification number: H01L28/10 ,  H01F5/00 ,  H01F17/0013 ,  H01F41/041 ,  H01L23/5227 ,  H01L23/525 ,  H01L24/10 ,  H01L24/13 ,  H01L27/08 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A system and method utilize a redistribution layer in a flip-chip or wirebond package, which is also used to route signals to bumps, as a layer for the construction of an on-chip inductor or a layer of a multiple-layer on-chip inductor. In one example, the redistribution layer is surrounded by dual-layer passivation to protect it, and the inductor formed thereby, from the environment and isolate it, and the inductor formed thereby, from the metal layer beneath it.

Abstract translation: 一种系统和方法利用倒装芯片或引线键合封装中的再分布层，其也用于将信号路由到凸点，作为用于构建片上电感器的层或多层片上层 电感。 在一个示例中，再分布层被双层钝化包围，以保护它，并且从环境形成的电感器从其环境中分离出来并将其与其形成的电感器从其下方的金属层隔离开来。

公开(公告)号：US20140191315A1

公开(公告)日：2014-07-10

申请号：US13737682

申请日：2013-01-09

Applicant: BROADCOM CORPORATION

Inventor： Akira Ito

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7831 ,  H01L29/66484 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/785

Abstract: A semiconductor device includes a first well and a second well implanted in a semiconductor substrate. The semiconductor device further includes a gate structure above the first and second wells between a raised source structure and a raised drain structure. The raised source structure above is in contact with the first well and connected with the gate structure through a first semiconductor fin structure. The raised drain structure above and in contact with the second well and connected with a second semiconductor fin structure. The second semiconductor fin structure includes at least a gap and a lightly doped portion.

Abstract translation: 半导体器件包括注入半导体衬底中的第一阱和第二阱。 该半导体器件还包括位于升高的源极结构和升高的漏极结构之间的第一和第二阱之上的栅极结构。 上述升高的源极结构与第一阱接触并通过第一半导体鳍结构与栅极结构连接。 上升的漏极结构在第二阱上方并与第二阱接触并与第二半导体鳍结构连接。 第二半导体鳍结构至少包括间隙和轻掺杂部分。

公开(公告)号：US20140183628A1

公开(公告)日：2014-07-03

申请号：US13728264

申请日：2012-12-27

Applicant: BROADCOM CORPORATION

Inventor： Akira Ito

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0882 ,  H01L29/0886 ,  H01L29/41775 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7835

Abstract: A semiconductor device includes a first well and a second well implanted in a semiconductor substrate. The semiconductor device further includes a raised drain structure above and in contact with the second well and separate from the gate structure. The raised drain structure includes a drain connection point above the surface of the second well.

Abstract translation: 半导体器件包括注入半导体衬底中的第一阱和第二阱。 半导体器件还包括在第二阱上方并与第二阱接触并与栅极结构分离的升高的漏极结构。 升高的漏极结构包括在第二阱的表面上方的漏极连接点。

公开(公告)号：US20130175613A1

公开(公告)日：2013-07-11

申请号：US13782427

申请日：2013-03-01

Applicant: Broadcom Corporation

Inventor： Akira Ito ,  Xiangdon Chen

IPC: H01L21/28 ,  H01L29/78

CPC classification number: H01L21/28008 ,  H01L21/28035 ,  H01L29/105 ,  H01L29/4916 ,  H01L29/517 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7835

Abstract: According to one embodiment, a semiconductor device comprises a high-k gate dielectric overlying a well region having a first conductivity type formed in a semiconductor body, and a semiconductor gate formed on the high-k gate dielectric. The semiconductor gate is lightly doped so as to have a second conductivity type opposite the first conductivity type. The disclosed semiconductor device, which may be an NMOS or PMOS device, can further comprise an isolation region formed in the semiconductor body between the semiconductor gate and a drain of the second conductivity type, and a drain extension well of the second conductivity type surrounding the isolation region in the semiconductor body. In one embodiment, the disclosed semiconductor device is fabricated as part of an integrated circuit including one or more CMOS logic devices.

Abstract translation: 根据一个实施例，半导体器件包括覆盖在半导体本体中形成的具有第一导电类型的阱区的高k栅极电介质和形成在高k栅极电介质上的半导体栅极。 半导体栅极被轻掺杂，以具有与第一导电类型相反的第二导电类型。 所公开的可以是NMOS或PMOS器件的半导体器件还可以包括形成在半导体本体中的半导体栅极和第二导电类型的漏极之间的隔离区域，以及包围第二导电类型的漏极延伸阱 半导体体中的隔离区。 在一个实施例中，所公开的半导体器件被制造为包括一个或多个CMOS逻辑器件的集成电路的一部分。