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123 条记录 (耗时 0.045 秒)

    Method for making a mask by forming a phase bar in an integrated circuit design layout
    32.
    发明授权
    Method for making a mask by forming a phase bar in an integrated circuit design layout 有权
    通过在集成电路设计布局中形成相位棒来制作掩模的方法

    公开(公告)号：US08850366B2

    公开(公告)日：2014-09-30

    申请号：US13564019

    申请日：2012-08-01

    申请人： Ru-Gun Liu ,  Shuo-Yen Chou ,  Hoi-Tou Ng ,  Ken-Hsien Hsieh ,  Yi-Yin Chen

    发明人： Ru-Gun Liu ,  Shuo-Yen Chou ,  Hoi-Tou Ng ,  Ken-Hsien Hsieh ,  Yi-Yin Chen

    IPC分类号： G06F17/50

    CPC分类号： G03F1/36 ,  G03F1/14 ,  G03F1/144 ,  G03F7/701 ,  G03F7/70433 ,  G03F7/70441 ,  G06F17/5068

    摘要： A method for making a mask for an integrated circuit (IC) design includes receiving an IC design layout having a plurality IC features and performing a targeted-feature-surrounding (TFS) checking operation to identify a targeted-feature-surrounding-location (TFSL) in the IC design layout. The method also includes inserting a phase-bar (PB) to the TFSL, performing an optical proximity correction (OPC) to the IC design layout having the PB to form a modified IC design layout and providing the modified IC design layout for fabrication of the mask.

    摘要翻译： 制造用于集成电路（IC）设计的掩模的方法包括接收具有多个IC特征的IC设计布局，并执行目标特征周围（TFS）检查操作以识别目标特征周围位置（TFSL ）在IC设计布局中。 该方法还包括将相位棒（PB）插入到TFSL中，对具有PB的IC设计布局执行光学邻近校正（OPC）以形成修改的IC设计布局，并提供修改的IC设计布局来制造 面具。

    Via-free interconnect structure with self-aligned metal line interconnections
    33.
    发明授权
    Via-free interconnect structure with self-aligned metal line interconnections 有权
    具有自对准金属线互连的无通孔互连结构

    公开(公告)号：US08779592B2

    公开(公告)日：2014-07-15

    申请号：US13461224

    申请日：2012-05-01

    申请人： Yu-Po Tang ,  Shih-Ming Chang ,  Ken-Hsien Hsieh ,  Ru-Gun Liu

    发明人： Yu-Po Tang ,  Shih-Ming Chang ,  Ken-Hsien Hsieh ,  Ru-Gun Liu

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L27/10 ,  H01L29/74

    CPC分类号： H01L21/76838 ,  H01L21/76897 ,  H01L23/522 ,  H01L23/5221 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a first conductive line disposed over a substrate. The first conductive line is located in a first interconnect layer and extends along a first direction. The semiconductor device includes a second conductive line and a third conductive line each extending along a second direction different from the first direction. The second and third conductive lines are located in a second interconnect layer that is different from the first interconnect layer. The second and third conductive lines are separated by a gap that is located over or below the first conductive line. The semiconductor device includes a fourth conductive line electrically coupling the second and third conductive lines together. The fourth conductive line is located in a third interconnect layer that is different from the first interconnect layer and the second interconnect layer.

    摘要翻译： 本发明提供一种半导体器件。 半导体器件包括设置在衬底上的第一导电线。 第一导线位于第一互连层中并沿着第一方向延伸。 半导体器件包括沿着与第一方向不同的第二方向延伸的第二导线和第三导线。 第二和第三导线位于与第一互连层不同的第二互连层中。 第二和第三导线被位于第一导电线之上或之下的间隙分开。 半导体器件包括将第二和第三导线电耦合在一起的第四导线。 第四导线位于与第一互连层和第二互连层不同的第三互连层中。

    Methodology of optical proximity correction optimization
    34.
    发明授权
    Methodology of optical proximity correction optimization 有权
    光学邻近校正优化方法

    公开(公告)号：US08631360B2

    公开(公告)日：2014-01-14

    申请号：US13448977

    申请日：2012-04-17

    申请人： Hung-Chun Wang ,  Ming-Hui Chih ,  Yu-Po Tang ,  Chia-Ping Chiang ,  Feng-Ju Chang ,  Cheng Kun Tsai ,  Wen-Chun Huang ,  Ru-Gun Liu

    发明人： Hung-Chun Wang ,  Ming-Hui Chih ,  Yu-Po Tang ,  Chia-Ping Chiang ,  Feng-Ju Chang ,  Cheng Kun Tsai ,  Wen-Chun Huang ,  Ru-Gun Liu

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G03F1/36 ,  G03F1/70

    摘要： A method for performing OPC and evaluating OPC solutions is disclosed. An exemplary method includes receiving a design database corresponding to an IC circuit mask. A first lithography simulation and evaluation is performed on the design database utilizing a first set of performance indexes. A modification is made to the design database based on a result of performing the first lithography simulation and evaluation. A second lithography simulation and evaluation is performed on the design database utilizing a second set of performance indexes to verify the modification. If necessary, the design database is modified again based on a result of the second lithography simulation and evaluation. The modified design database is provided to a mask manufacturer for manufacturing the mask corresponding to the modified design database.

    摘要翻译： 公开了一种执行OPC和评估OPC解决方案的方法。 一种示例性方法包括接收对应于IC电路掩码的设计数据库。 使用第一组性能指标对设计数据库执行第一光刻模拟和评估。 基于执行第一光刻仿真和评估的结果对设计数据库进行修改。 使用第二组性能指标对设计数据库执行第二次光刻模拟和评估，以验证修改。 如果需要，基于第二光刻模拟和评估的结果再次修改设计数据库。 将修改后的设计数据库提供给掩模制造商以制造与修改的设计数据库相对应的掩模。

    FRACTURE AWARE OPC
    35.
    发明申请
    FRACTURE AWARE OPC 有权

    公开(公告)号：US20140013287A1

    公开(公告)日：2014-01-09

    申请号：US13544014

    申请日：2012-07-09

    申请人： Nian-Fuh Cheng ,  Yu-Po Tang ,  Chien-Fu Lee ,  Sheng-Wen Lin ,  Yong-Cheng Lin ,  Wen-Chun Huang ,  Ru-Gun Liu

    发明人： Nian-Fuh Cheng ,  Yu-Po Tang ,  Chien-Fu Lee ,  Sheng-Wen Lin ,  Yong-Cheng Lin ,  Wen-Chun Huang ,  Ru-Gun Liu

    IPC分类号： G06F17/50

    CPC分类号： G03F7/70441 ,  G03F1/36 ,  G03F1/70

    摘要： The present disclosure describes an OPC method of preparing data for forming a mask. The method includes setting a plurality of dissection points at the main feature and further includes setting a target point at the main feature. The method includes arranging the two dissection points crossing the main feature symmetrically each other. The method includes separating two adjacent dissection points at one side of the main feature by a maximum resolution of the mask writer. The method includes dividing the main feature into a plurality of segments using the dissection points. The method includes performing an OPC convergence simulation to a target point. The method includes correcting the segments belonging to an ambit of the target point and further includes correcting the segment shared by two ambits.

    摘要翻译： 本公开描述了制备用于形成掩模的数据的OPC方法。 该方法包括在主要特征处设置多个解剖点，并且还包括在主要特征处设置目标点。 该方法包括将两个解剖点布置成彼此对称的主要特征。 该方法包括通过掩模写入器的最大分辨率在主要特征的一侧分离两个相邻的解剖点。 该方法包括使用解剖点将主要特征划分成多个段。 该方法包括对目标点执行OPC收敛模拟。 该方法包括校正属于目标点的范围的段，并且还包括校正由两个方位共享的段。

    SEMICONDUCTOR INTERCONNECT STRUCTURE
    36.
    发明申请
    SEMICONDUCTOR INTERCONNECT STRUCTURE 审中-公开

    公开(公告)号：US20130292841A1

    公开(公告)日：2013-11-07

    申请号：US13464055

    申请日：2012-05-04

    申请人： Chih-Ming Lai ,  Wen-Chun Huang ,  Ru-Gun Liu ,  Pi-Tsung Chen

    发明人： Chih-Ming Lai ,  Wen-Chun Huang ,  Ru-Gun Liu ,  Pi-Tsung Chen

    IPC分类号： H01L21/768 ,  H01L23/48

    CPC分类号： H01L23/5226 ,  H01L21/76816 ,  H01L23/5283 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present disclosure provides an interconnect structure for a semiconductor device. The interconnect structure includes a first metal layer that contains a first metal line. The interconnect structure includes a dielectric layer located over the first metal layer. The dielectric layer contains a first sub-via electrically coupled to the first metal line and a second sub-via electrically coupled to the first sub-via. The second sub-via is different from the first sub-via. The interconnect structure includes a second metal layer located over the dielectric layer. The second metal layer contains a second metal line electrically coupled to the second sub-via. No other metal layer is located between the first metal layer and the second metal layer.

    摘要翻译： 本公开提供了一种用于半导体器件的互连结构。 互连结构包括含有第一金属线的第一金属层。 互连结构包括位于第一金属层上方的电介质层。 电介质层包含电耦合到第一金属线的第一子通路和电耦合到第一子通路的第二子通路。 第二子通孔不同于第一子通孔。 互连结构包括位于电介质层上方的第二金属层。 第二金属层包含电耦合到第二子通孔的第二金属线。 第一金属层和第二金属层之间没有其他金属层。

    Semiconductor Device With Self-Aligned Interconnects and Blocking Portions
    37.
    发明申请
    Semiconductor Device With Self-Aligned Interconnects and Blocking Portions 有权
    具有自对准互连和阻塞部分的半导体器件

    公开(公告)号：US20130285246A1

    公开(公告)日：2013-10-31

    申请号：US13458396

    申请日：2012-04-27

    申请人： Shih-Ming Chang ,  Ken-Hsien Hsieh ,  Tsong-Hua Ou ,  Ru-Gun Liu ,  Fang-Yu Fan ,  Yuan-Te Hou

    发明人： Shih-Ming Chang ,  Ken-Hsien Hsieh ,  Tsong-Hua Ou ,  Ru-Gun Liu ,  Fang-Yu Fan ,  Yuan-Te Hou

    IPC分类号： H01L23/522 ,  H01L21/768

    CPC分类号： H01L23/522 ,  H01L21/76801 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76897 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A device and method for fabricating a device is disclosed. An exemplary device includes a first conductive layer disposed over a substrate, the first conductive layer including a first plurality of conductive lines extending in a first direction. The device further includes a second conductive layer disposed over the first conductive layer, the second conductive layer including a second plurality of conductive lines extending in a second direction. The device further includes a self-aligned interconnect formed at an interface where a first conductive line of the first plurality of conductive lines is in electrical contact with a first conductive line of the second plurality of conductive lines. The device further includes a blocking portion interposed between a second conductive line of the first plurality of conductive lines and a second conductive line of the second plurality of conductive lines.

    摘要翻译： 公开了一种用于制造装置的装置和方法。 示例性器件包括设置在衬底上的第一导电层，第一导电层包括沿第一方向延伸的第一多个导电线。 该装置还包括设置在第一导电层上的第二导电层，第二导电层包括沿第二方向延伸的第二多个导电线。 该装置还包括形成在第一多个导线的第一导线与第二多个导线的第一导线电接触的界面处的自对准互连。 该装置还包括插入在第一多个导线中的第二导线与第二多个导线之间的第二导线之间的阻挡部分。

    Mask-shift-aware RC extraction for double patterning design
    38.
    发明授权
    Mask-shift-aware RC extraction for double patterning design 有权
    面罩移位感知RC提取双图案设计

    公开(公告)号：US08119310B1

    公开(公告)日：2012-02-21

    申请号：US12872938

    申请日：2010-08-31

    申请人： Lee-Chung Lu ,  Yi-Kan Cheng ,  Hsiao-Shu Chao ,  Ke-Ying Su ,  Cheng-Hung Yeh ,  Dian-Hau Chen ,  Ru-Gun Liu ,  Wen-Chun Huang

    发明人： Lee-Chung Lu ,  Yi-Kan Cheng ,  Hsiao-Shu Chao ,  Ke-Ying Su ,  Cheng-Hung Yeh ,  Dian-Hau Chen ,  Ru-Gun Liu ,  Wen-Chun Huang

    IPC分类号： G03F9/00 ,  G06F17/50

    CPC分类号： G03F1/70

    摘要： A method includes providing a layout of an integrated circuit design, and generating a plurality of double patterning decompositions from the layout, with each of the plurality of double patterning decompositions including patterns separated to a first mask and a second mask of a double patterning mask set. A maximum shift between the first and the second masks is determined, wherein the maximum shift is a maximum expected mask shift in a manufacturing process for implementing the layout on a wafer. For each of the plurality of double patterning decompositions, a worst-case performance value is simulated using mask shifts within a range defined by the maximum shift.

    摘要翻译： 一种方法包括提供集成电路设计的布局，以及从布局生成多个双重图案化分解，多个双重图案化分解中的每一个包括分离到第一掩模的图案和双图案掩模组的第二掩模 。 确定第一和第二掩模之间的最大偏移，其中最大偏移是用于在晶片上实现布局的制造过程中的最大预期掩模移位。 对于多个双重图案化分解中的每一个，使用由最大偏移限定的范围内的掩模移位来模拟最坏情况的性能值。

    METHOD, SYSTEM, AND APPARATUS FOR ADJUSTING LOCAL AND GLOBAL PATTERN DENSITY OF AN INTEGRATED CIRCUIT DESIGN
    40.
    发明申请
    METHOD, SYSTEM, AND APPARATUS FOR ADJUSTING LOCAL AND GLOBAL PATTERN DENSITY OF AN INTEGRATED CIRCUIT DESIGN 有权
    用于调整集成电路设计的局部和全局模式密度的方法，系统和装置

    公开(公告)号：US20110204470A1

    公开(公告)日：2011-08-25

    申请号：US12712665

    申请日：2010-02-25

    申请人： Ying-Chou Cheng ,  Cheng-Lung Tsai ,  Tsong-Hua Ou ,  Cheng Kun Tsai ,  Ru-Gun Liu ,  Wen-Chun Huang

    发明人： Ying-Chou Cheng ,  Cheng-Lung Tsai ,  Tsong-Hua Ou ,  Cheng Kun Tsai ,  Ru-Gun Liu ,  Wen-Chun Huang

    IPC分类号： H01L23/544 ,  G06F17/50

    CPC分类号： G06F17/5068

    摘要： An integrated circuit (IC) design method providing a circuit design layout having a plurality of functional blocks disposed a distance away from each other; identifying a local pattern density to an approximate dummy region, on the circuit design layout, within a predefined distance to one of the functional blocks; performing a local dummy insertion to the approximate dummy region according to the local pattern density; repeating the identifying and performing to at least some other of the functional blocks; and implementing a global dummy insertion to a non-local dummy region according to a global pattern density.

    摘要翻译： 一种提供电路设计布局的集成电路（IC）设计方法，其具有彼此远离设置的多个功能块; 将电路设计布局上的近似虚拟区域的局部图案密度识别在与功能块之一预定义的距离内; 根据局部图案密度对近似虚拟区进行局部虚拟插入; 重复对所述功能块中的至少一些其他功能块的识别和执行; 并且根据全局模式密度对非局部虚拟区域实施全局虚拟插入。