公开(公告)号：US06969912B2

公开(公告)日：2005-11-29

申请号：US10713804

申请日：2003-11-14

申请人： Uei-Ming Jow ,  Pei-Shen Wei ,  Ching-Liang Weng ,  Chun-Kun Wu ,  Chang-Sheng Chen ,  Ying-Jiunn Lai

发明人： Uei-Ming Jow ,  Pei-Shen Wei ,  Ching-Liang Weng ,  Chun-Kun Wu ,  Chang-Sheng Chen ,  Ying-Jiunn Lai

IPC分类号： H01L21/4763 ,  H01L23/053 ,  H01L23/48 ,  H05K1/02 ,  H05K1/16 ,  H05K3/46

CPC分类号： H05K1/162 ,  H05K1/0218 ,  H05K1/0219 ,  H05K3/4602 ,  H05K2201/0723 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/09672

摘要： An embedded microelectronic capacitor incorporating at least one ground shielding layer is provided which includes an upper ground shielding layer that has an aperture therethrough; an electrode plate positioned spaced-apart from the upper ground shielding layer that has a via extending upwardly away from the electrode plate through the aperture in the upper ground shielding layer providing electrical communication to the electrode plate without shorting to the upper ground shielding layer; a middle ground shielding layer positioned in the same plane of the electrode plate, surrounding while spaced-apart from the electrode plate at a predetermined distance; a lower ground shielding layer positioned spaced-apart from the electrode plate in an opposing relationship to the upper ground shielding layer; and a dielectric material embedding the upper ground shielding layer; the middle ground shielding layer and the lower ground shielding layer.

摘要翻译： 提供了包括至少一个接地屏蔽层的嵌入式微电子电容器，其包括具有穿过其中的孔的上接地屏蔽层; 与所述上接地屏蔽层间隔开的电极板，所述电极板具有通过所述上接地屏蔽层中的孔向上远离所述电极板延伸的通孔，所述通孔提供与所述电极板的电连通而不与所述上接地屏蔽层短路; 位于电极板的同一平面中的中间屏蔽层，以与预定距离的电极板隔开间隔开; 与所述上接地屏蔽层相对的位置与所述电极板隔开定位的下接地屏蔽层; 以及嵌入上接地屏蔽层的电介质材料; 中间接地屏蔽层和下部接地屏蔽层。

公开(公告)号：US07948355B2

公开(公告)日：2011-05-24

申请号：US11852244

申请日：2007-09-07

申请人： Chang-Lin Wei ,  Chang-Sheng Chen ,  Cheng-Hua Tsai ,  Syun Yu ,  Chin-Sun Shyu

发明人： Chang-Lin Wei ,  Chang-Sheng Chen ,  Cheng-Hua Tsai ,  Syun Yu ,  Chin-Sun Shyu

IPC分类号： H01C1/012

CPC分类号： H05K1/167 ,  H05K1/0237 ,  H05K1/0298 ,  H05K2201/09781

摘要： An embedded resistor device includes a resistor, a ground plane located near a first side of the resistor and electrically coupled to a first end of the resistor, at the ground plane a hole is provided, a first dielectric layer exists between the resistor and the ground plane, a conductive wire, which is electrically coupled to a second end of the resistor different from the first end of the resistor and partially surrounds the resistor, is used as an auxiliary for supporting a resistor-coating process of the resistor and to provide a terminal of the embedded resistor device at the conductive wire, a conductive region located near a second side of the ground plane different from the first side of the resistor, a second dielectric layer exists between the ground plane and the conductive region, and a conductive path to electrically couple the conductive wire to the conductive region through the hole.

摘要翻译： 嵌入式电阻器件包括电阻器，接地平面位于电阻器的第一侧附近并电耦合到电阻器的第一端，在接地平面处设有一个孔，第一电介质层位于电阻器和地之间 平面，电耦合到电阻器的不同于电阻器的第一端并部分地围绕电阻器的第二端的导线被用作支持电阻器的电阻器涂覆工艺的辅助件，并且提供 在导电线处的嵌入式电阻器件的端子，位于接地平面的与电阻器的第一侧不同的第二侧附近的导电区域，在接地平面和导电区域之间存在第二介电层，并且导电路径 以通过该孔将导线电连接到导电区域。

公开(公告)号：US20080290984A1

公开(公告)日：2008-11-27

申请号：US11852244

申请日：2007-09-07

申请人： Chang-Lin Wei ,  Chang-Sheng Chen ,  Cheng-Hua Tsai ,  Syun Yu ,  Chin-Sun Shyu

发明人： Chang-Lin Wei ,  Chang-Sheng Chen ,  Cheng-Hua Tsai ,  Syun Yu ,  Chin-Sun Shyu

IPC分类号： H01C1/02

CPC分类号： H05K1/167 ,  H05K1/0237 ,  H05K1/0298 ,  H05K2201/09781

摘要： An embedded resistor device includes a resistor, a ground plane located near a first side of the resistor and electrically coupled to a first end of the resistor, at the ground plane a hole is provided, a first dielectric layer exists between the resistor and the ground plane, a conductive wire, which is electrically coupled to a second end of the resistor different from the first end of the resistor and partially surrounds the resistor, is used as an auxiliary for supporting a resistor-coating process of the resistor and to provide a terminal of the embedded resistor device at the conductive wire, a conductive region located near a second side of the ground plane different from the first side of the resistor, a second dielectric layer exists between the ground plane and the conductive region, and a conductive path to electrically couple the conductive wire to the conductive region through the hole.

摘要翻译： 嵌入式电阻器件包括电阻器，接地平面位于电阻器的第一侧附近并电耦合到电阻器的第一端，在接地平面处设有一个孔，第一电介质层位于电阻器和地之间 平面，电耦合到电阻器的不同于电阻器的第一端并部分地围绕电阻器的第二端的导线被用作支持电阻器的电阻器涂覆工艺的辅助件，并且提供 在导电线处的嵌入式电阻器件的端子，位于接地平面的与电阻器的第一侧不同的第二侧附近的导电区域，在接地平面和导电区域之间存在第二介电层，并且导电路径 以通过该孔将导线电连接到导电区域。

公开(公告)号：US08179695B2

公开(公告)日：2012-05-15

申请号：US12783478

申请日：2010-05-19

申请人： Uei-Ming Jow ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Min-Lin Lee ,  Shinn-Juh Lai

发明人： Uei-Ming Jow ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Min-Lin Lee ,  Shinn-Juh Lai

IPC分类号： H05K9/00

CPC分类号： H05K1/0218 ,  H05K1/0224 ,  H05K1/0237 ,  H05K1/025 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K2201/0792 ,  H05K2201/09672

摘要： A mirror image shielding structure is provided, which includes an electronic element and a ground shielding plane below the electronic element. The shape of the ground shielding plane is identical to the projection shape of the electronic element, and the horizontal size of the ground shielding plane is greater than or equal to that of the electronic element. Thus, the parasitic effect between the electronic element and the ground shielding plane is effectively reduced, and the vertical coupling effect between electronic elements is also reduced. Furthermore, the vertical impact on the signal integrity of the embedded elements caused by the layout of the transmission lines is prevented.

摘要翻译： 提供一种镜像屏蔽结构，其包括电子元件和电子元件下方的接地屏蔽平面。 接地屏蔽面的形状与电子元件的突出形状相同，接地屏蔽面的水平尺寸大于或等于电子元件的尺寸。 因此，有效地减小了电子元件与接地屏蔽层之间的寄生效应，并且电子元件之间的垂直耦合效应也降低。 此外，防止了由传输线的布局引起的对嵌入元件的信号完整性的垂直影响。

公开(公告)号：US20070183131A1

公开(公告)日：2007-08-09

申请号：US11451292

申请日：2006-06-12

申请人： Uei-Ming Jow ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Min-Lin Lee ,  Shinn-Juh Lai

发明人： Uei-Ming Jow ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Min-Lin Lee ,  Shinn-Juh Lai

IPC分类号： H04B3/28 ,  H05K9/00

CPC分类号： H05K1/0218 ,  H05K1/0224 ,  H05K1/0237 ,  H05K1/025 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K2201/0792 ,  H05K2201/09672

摘要： A mirror image shielding structure is provided, which includes an electronic element and a ground shielding plane below the electronic element. The shape of the ground shielding plane is identical to the projection shape of the electronic element, and the horizontal size of the ground shielding plane is greater than or equal to that of the electronic element. Thus, the parasitic effect between the electronic element and the ground shielding plane is effectively reduced, and the vertical coupling effect between electronic elements is also reduced. Furthermore, the vertical impact on the signal integrity of the embedded elements caused by the layout of the transmission lines is prevented.

摘要翻译： 提供一种镜像屏蔽结构，其包括电子元件和电子元件下方的接地屏蔽平面。 接地屏蔽面的形状与电子元件的突出形状相同，接地屏蔽面的水平尺寸大于或等于电子元件的尺寸。 因此，有效地减小了电子元件与接地屏蔽层之间的寄生效应，并且电子元件之间的垂直耦合效应也降低。 此外，防止了由传输线的布局引起的对嵌入元件的信号完整性的垂直影响。

公开(公告)号：US07714590B2

公开(公告)日：2010-05-11

申请号：US11708935

申请日：2007-02-20

申请人： Uei-Ming Jow ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Chin-Sun Shyu ,  Chang-Sheng Chen

发明人： Uei-Ming Jow ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Chin-Sun Shyu ,  Chang-Sheng Chen

IPC分类号： G01R31/12 ,  G01R31/02 ,  H01G4/30 ,  H01G4/228

CPC分类号： H05K1/0268 ,  G01R31/2818 ,  H05K1/0298 ,  H05K1/116 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167

摘要： A method is provided for testing a built-in component including multiple terminals in a multi-layered circuit board. At least one signal pad is provided on a top surface of the multi-layered circuit board for signal transmission. Each of the signal pads are electrically connected to one of the multiple terminals. At least one test pad is provided on the top surface of the multi-layered circuit board and each of the test pads is electrically connected to one of the multiple terminals. Then, detection occurs regarding one of the signal pads and one of the test pads that are electrically connected to a same one of the multiple terminals in order to determine a connection status of an electric path extending from the one signal pad through the same one terminal to the one test pad.

摘要翻译： 提供一种用于在多层电路板中测试包括多个端子的内置组件的方法。 在用于信号传输的多层电路板的顶表面上提供至少一个信号焊盘。 每个信号焊盘电连接到多个端子中的一个。 在多层电路板的顶表面上提供至少一个测试焊盘，并且每个测试焊盘电连接到多个端子之一。 然后，对于电连接到多个端子中的一个的一个信号焊盘和测试焊盘之一进行检测，以便确定从一个信号焊盘延伸通过相同的一个端子的电通路的连接状态 到一个测试垫。

公开(公告)号：US07446711B2

公开(公告)日：2008-11-04

申请号：US11555107

申请日：2006-10-31

申请人： Uei-Ming Jow ,  Chang-Sheng Chen

发明人： Uei-Ming Jow ,  Chang-Sheng Chen

IPC分类号： H01Q1/38

CPC分类号： H01Q1/38 ,  H01Q9/0407 ,  H01Q9/0485

摘要： A high dielectric antenna substrate and antenna thereof are provided. The substrate includes a first dielectric layer having a first dielectric constant, and a second dielectric layer having a second dielectric constant. The second dielectric layer is formed on one surface of the first dielectric layer. The second dielectric constant is lower than the first dielectric constant. Furthermore, a first metal layer and a second metal layer are optionally formed on the same surface or two surfaces of the first dielectric layer to compose a capacitor.

摘要翻译： 提供了高介电天线基板及其天线。 衬底包括具有第一介电常数的第一电介质层和具有第二介电常数的第二电介质层。 第二电介质层形成在第一电介质层的一个表面上。 第二介电常数低于第一介电常数。 此外，第一金属层和第二金属层可选地形成在第一介电层的相同表面或两个表面上以构成电容器。

公开(公告)号：US20080136574A1

公开(公告)日：2008-06-12

申请号：US11871896

申请日：2007-10-12

申请人： Uei-Ming Jow ,  Chang-Sheng Chen ,  Chin-Sun Shyu

发明人： Uei-Ming Jow ,  Chang-Sheng Chen ,  Chin-Sun Shyu

IPC分类号： H01F27/28 ,  H01F41/04 ,  H01F5/00

CPC分类号： H01F17/0006 ,  H01F41/041 ,  H01F2017/0066 ,  Y10T29/4902

摘要： Embedded inductor devices and fabrication methods thereof. An embedded inductor device includes a substrate, a conductive coil disposed on the substrate, and a patterned high-permeability (μr>1) magnetic layer on the substrate. The patterned high-permeability (μr>1) magnetic layer physically contacts the conductive coil. The conductive coil and the patterned high-permeability (μr>1) magnetic layer are intersected and substantially perpendicular to each other.

摘要翻译： 嵌入式电感器件及其制造方法。 嵌入式电感器件包括衬底，设置在衬底上的导电线圈和在衬底上的图案化高磁导率（μLr 1）磁性层。 图案化的高磁导率（μLr/ 1）磁性层物理地接触导电线圈。 导电线圈和图案化的高磁导率磁性层彼此相交并基本上垂直。

公开(公告)号：US07345366B2

公开(公告)日：2008-03-18

申请号：US11131741

申请日：2005-05-18

申请人： Uei-Ming Jow ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Chin-Sun Shyu ,  Chang-Sheng Chen

发明人： Uei-Ming Jow ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Chin-Sun Shyu ,  Chang-Sheng Chen

IPC分类号： H01L23/48 ,  H01L23/58 ,  G01R31/26

CPC分类号： H05K1/0268 ,  G01R31/2818 ,  H05K1/0298 ,  H05K1/116 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167

摘要： A multi-layered circuit board a built-in component including multiple terminals, at least one signal pad formed on a top surface of the multi-layered circuit board for signal transmission, each of the at least one signal pad corresponding to one of the multiple terminals, and at least one test pad formed on the top surface of the multi-layered circuit board, each of the at least one test pad corresponding to one of the at least one signal pad for testing an electric path extending from the one signal pad through the one terminal to the each of the at least one test pad.

摘要翻译： 一种多层电路板，包括多个端子的内置组件，至少一个形成在用于信号传输的多层电路板的顶表面上的信号焊盘，所述至少一个信号焊盘中的每一个对应于多个 端子和形成在多层电路板的顶表面上的至少一个测试焊盘，所述至少一个测试焊盘中的每一个对应于至少一个信号焊盘中的一个，用于测试从一个信号焊盘延伸的电路径 通过所述一个端子到所述至少一个测试垫中的每一个。

公开(公告)号：US07308377B2

公开(公告)日：2007-12-11

申请号：US11591381

申请日：2006-11-01

申请人： Uei-Ming Jow ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Min-Lin Lee ,  Shinn-Juh Lai

发明人： Uei-Ming Jow ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Min-Lin Lee ,  Shinn-Juh Lai

IPC分类号： G01V1/00

CPC分类号： G01R31/2818 ,  G01R31/2805 ,  G01R31/304

摘要： A test method of an embedded capacitor and test system thereof are provided. The method and system are used to determine an electrical specification of the embedded capacitive component in a circuit board substrate, thereby avoiding executing a follow-up fabricating process for the circuit board substrate not satisfying the desired specification. In the method and system, a geometric size of the embedded capacitor is measured, and a relation value between the electrical parameter and the geometric size and a standard electrical parameter are obtained from a model database, to calculate the electrical parameter of the embedded capacitor. Then, the electrical parameter of the embedded capacitor is compared with the standard electrical parameter, to obtain an error value. Therefore, according to the error value, it may be acquired whether or not the circuit board substrate satisfies set electrical specifications.