利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

67 条记录 (耗时 0.028 秒)

    Mirror image shielding structure
    1.
    发明授权
    Mirror image shielding structure 有权
    镜像屏蔽结构

    公开(公告)号：US08179695B2

    公开(公告)日：2012-05-15

    申请号：US12783478

    申请日：2010-05-19

    申请人： Uei-Ming Jow ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Min-Lin Lee ,  Shinn-Juh Lai

    发明人： Uei-Ming Jow ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Min-Lin Lee ,  Shinn-Juh Lai

    IPC分类号： H05K9/00

    CPC分类号： H05K1/0218 ,  H05K1/0224 ,  H05K1/0237 ,  H05K1/025 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K2201/0792 ,  H05K2201/09672

    摘要： A mirror image shielding structure is provided, which includes an electronic element and a ground shielding plane below the electronic element. The shape of the ground shielding plane is identical to the projection shape of the electronic element, and the horizontal size of the ground shielding plane is greater than or equal to that of the electronic element. Thus, the parasitic effect between the electronic element and the ground shielding plane is effectively reduced, and the vertical coupling effect between electronic elements is also reduced. Furthermore, the vertical impact on the signal integrity of the embedded elements caused by the layout of the transmission lines is prevented.

    摘要翻译： 提供一种镜像屏蔽结构，其包括电子元件和电子元件下方的接地屏蔽平面。 接地屏蔽面的形状与电子元件的突出形状相同，接地屏蔽面的水平尺寸大于或等于电子元件的尺寸。 因此，有效地减小了电子元件与接地屏蔽层之间的寄生效应，并且电子元件之间的垂直耦合效应也降低。 此外，防止了由传输线的布局引起的对嵌入元件的信号完整性的垂直影响。

    Mirror image shielding structure
    2.
    发明申请
    Mirror image shielding structure 有权
    镜像屏蔽结构

    公开(公告)号：US20070183131A1

    公开(公告)日：2007-08-09

    申请号：US11451292

    申请日：2006-06-12

    申请人： Uei-Ming Jow ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Min-Lin Lee ,  Shinn-Juh Lai

    发明人： Uei-Ming Jow ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Min-Lin Lee ,  Shinn-Juh Lai

    IPC分类号： H04B3/28 ,  H05K9/00

    CPC分类号： H05K1/0218 ,  H05K1/0224 ,  H05K1/0237 ,  H05K1/025 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K2201/0792 ,  H05K2201/09672

    摘要： A mirror image shielding structure is provided, which includes an electronic element and a ground shielding plane below the electronic element. The shape of the ground shielding plane is identical to the projection shape of the electronic element, and the horizontal size of the ground shielding plane is greater than or equal to that of the electronic element. Thus, the parasitic effect between the electronic element and the ground shielding plane is effectively reduced, and the vertical coupling effect between electronic elements is also reduced. Furthermore, the vertical impact on the signal integrity of the embedded elements caused by the layout of the transmission lines is prevented.

    摘要翻译： 提供一种镜像屏蔽结构，其包括电子元件和电子元件下方的接地屏蔽平面。 接地屏蔽面的形状与电子元件的突出形状相同，接地屏蔽面的水平尺寸大于或等于电子元件的尺寸。 因此，有效地减小了电子元件与接地屏蔽层之间的寄生效应，并且电子元件之间的垂直耦合效应也降低。 此外，防止了由传输线的布局引起的对嵌入元件的信号完整性的垂直影响。

    MIRROR IMAGE SHIELDING STRUCTURE
    3.
    发明申请
    MIRROR IMAGE SHIELDING STRUCTURE 有权
    镜像图像屏蔽结构

    公开(公告)号：US20100226112A1

    公开(公告)日：2010-09-09

    申请号：US12783478

    申请日：2010-05-19

    申请人： Uei-Ming Jow ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Min-Lin Lee ,  Shinn-Juh Lai

    发明人： Uei-Ming Jow ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Min-Lin Lee ,  Shinn-Juh Lai

    IPC分类号： H05K9/00

    CPC分类号： H05K1/0218 ,  H05K1/0224 ,  H05K1/0237 ,  H05K1/025 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K2201/0792 ,  H05K2201/09672

    摘要： A mirror image shielding structure is provided, which includes an electronic element and a ground shielding plane below the electronic element. The shape of the ground shielding plane is identical to the projection shape of the electronic element, and the horizontal size of the ground shielding plane is greater than or equal to that of the electronic element. Thus, the parasitic effect between the electronic element and the ground shielding plane is effectively reduced, and the vertical coupling effect between electronic elements is also reduced. Furthermore, the vertical impact on the signal integrity of the embedded elements caused by the layout of the transmission lines is prevented.

    摘要翻译： 提供一种镜像屏蔽结构，其包括电子元件和电子元件下方的接地屏蔽平面。 接地屏蔽面的形状与电子元件的突出形状相同，接地屏蔽面的水平尺寸大于或等于电子元件的尺寸。 因此，有效地减小了电子元件与接地屏蔽层之间的寄生效应，并且电子元件之间的垂直耦合效应也降低。 此外，防止了由传输线的布局引起的对嵌入元件的信号完整性的垂直影响。

    Mirror image shielding structure
    4.
    发明授权
    Mirror image shielding structure 有权
    镜像屏蔽结构

    公开(公告)号：US07764512B2

    公开(公告)日：2010-07-27

    申请号：US11451292

    申请日：2006-06-12

    申请人： Uei-Ming Jow ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Min-Lin Lee ,  Shinn-Juh Lai

    发明人： Uei-Ming Jow ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Min-Lin Lee ,  Shinn-Juh Lai

    IPC分类号： H05K7/18

    CPC分类号： H05K1/0218 ,  H05K1/0224 ,  H05K1/0237 ,  H05K1/025 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K2201/0792 ,  H05K2201/09672

    摘要： A mirror image shielding structure is provided, which includes an electronic element and a ground shielding plane below the electronic element. The shape of the ground shielding plane is identical to the projection shape of the electronic element, and the horizontal size of the ground shielding plane is greater than or equal to that of the electronic element. Thus, the parasitic effect between the electronic element and the ground shielding plane is effectively reduced, and the vertical coupling effect between electronic elements is also reduced. Furthermore, the vertical impact on the signal integrity of the embedded elements caused by the layout of the transmission lines is prevented.

    摘要翻译： 提供一种镜像屏蔽结构，其包括电子元件和电子元件下方的接地屏蔽平面。 接地屏蔽面的形状与电子元件的突出形状相同，接地屏蔽面的水平尺寸大于或等于电子元件的尺寸。 因此，有效地减小了电子元件与接地屏蔽层之间的寄生效应，并且电子元件之间的垂直耦合效应也降低。 此外，防止了由传输线的布局引起的对嵌入元件的信号完整性的垂直影响。

    Test method of embedded capacitor and test system thereof
    7.
    发明授权
    Test method of embedded capacitor and test system thereof 失效

    公开(公告)号：US07308377B2

    公开(公告)日：2007-12-11

    申请号：US11591381

    申请日：2006-11-01

    申请人： Uei-Ming Jow ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Min-Lin Lee ,  Shinn-Juh Lai

    发明人： Uei-Ming Jow ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Min-Lin Lee ,  Shinn-Juh Lai

    IPC分类号： G01V1/00

    CPC分类号： G01R31/2818 ,  G01R31/2805 ,  G01R31/304

    摘要： A test method of an embedded capacitor and test system thereof are provided. The method and system are used to determine an electrical specification of the embedded capacitive component in a circuit board substrate, thereby avoiding executing a follow-up fabricating process for the circuit board substrate not satisfying the desired specification. In the method and system, a geometric size of the embedded capacitor is measured, and a relation value between the electrical parameter and the geometric size and a standard electrical parameter are obtained from a model database, to calculate the electrical parameter of the embedded capacitor. Then, the electrical parameter of the embedded capacitor is compared with the standard electrical parameter, to obtain an error value. Therefore, according to the error value, it may be acquired whether or not the circuit board substrate satisfies set electrical specifications.

    Test method of embedded capacitor and test system thereof
    8.
    发明申请
    Test method of embedded capacitor and test system thereof 失效
    嵌入式电容器的测试方法及其测试系统

    公开(公告)号：US20070168148A1

    公开(公告)日：2007-07-19

    申请号：US11591381

    申请日：2006-11-01

    申请人： Uei-Ming Jow ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Min-Lin Lee ,  Shinn-Juh Lai

    发明人： Uei-Ming Jow ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Min-Lin Lee ,  Shinn-Juh Lai

    IPC分类号： G06F19/00 ,  G01R31/00

    CPC分类号： G01R31/2818 ,  G01R31/2805 ,  G01R31/304

    摘要： A test method of an embedded capacitor and test system thereof are provided. The method and system are used to determine an electrical specification of the embedded capacitive component in a circuit board substrate, thereby avoiding executing a follow-up fabricating process for the circuit board substrate not satisfying the desired specification. In the method and system, a geometric size of the embedded capacitor is measured, and a relation value between the electrical parameter and the geometric size and a standard electrical parameter are obtained from a model database, to calculate the electrical parameter of the embedded capacitor. Then, the electrical parameter of the embedded capacitor is compared with the standard electrical parameter, to obtain an error value. Therefore, according to the error value, it may be acquired whether or not the circuit board substrate satisfies set electrical specifications.

    摘要翻译： 提供了一种嵌入式电容器及其测试系统的测试方法。 该方法和系统用于确定电路板基板中的嵌入式电容元件的电气规格，从而避免执行不满足期望规格的电路板基板的后续制造工艺。 在该方法和系统中，测量嵌入式电容器的几何尺寸，并从模型数据库中获得电参数和几何尺寸之间的关系值以及标准电参数，以计算嵌入式电容器的电参数。 然后，将嵌入式电容器的电气参数与标准电气参数进行比较，以获得误差值。 因此，根据误差值，可以获取电路板基板是否满足设定的电气规格。

    Complementary mirror image embedded planar resistor architecture
    9.
    发明授权
    Complementary mirror image embedded planar resistor architecture 有权
    互补镜像嵌入式平面电阻架构

    公开(公告)号：US08035036B2

    公开(公告)日：2011-10-11

    申请号：US11861297

    申请日：2007-09-26

    申请人： Uei-Ming Jow ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Ying-Jiunn Lai

    发明人： Uei-Ming Jow ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Ying-Jiunn Lai

    IPC分类号： H05K1/16

    CPC分类号： H05K1/167 ,  H05K1/0224 ,  H05K1/025 ,  H05K1/0298 ,  H05K2201/0792 ,  H05K2201/09681 ,  H05K2201/0969

    摘要： A complementary mirror image embedded planar resistor architecture is provided. In the architecture, a complementary hollow structure is formed on a ground plane or an electrode plane to minimize the parasitic resistance, so as to efficiently enhance the application frequency. In addition, in some cases, some signal transmission lines pass through the position below the embedded planar resistor, and if there is no shield at all, serious interference or cross talk phenomenon occurs. Therefore, the complementary hollow structure of the ground plane, the electrode plane, or a power layer adjacent to the embedded planar resistor is designed to be a mesh structure, so as to reduce the interference or cross talk phenomenon. In this manner, the whole resistor structure has preferable high frequency electrical characteristic in the circuit.

    摘要翻译： 提供了一种互补镜像嵌入式平面电阻架构。 在该结构中，在接地平面或电极平面上形成互补的中空结构以最小化寄生电阻，从而有效地提高施加频率。 此外，在某些情况下，一些信号传输线通过嵌入式平面电阻器下方的位置，如果根本没有屏蔽，则会发生严重的干扰或串扰现象。 因此，将接地平面，电极平面或与嵌入式平面电阻器相邻的功率层的互补空心结构设计为网格结构，以减少干扰或串扰现象。 以这种方式，整个电阻器结构在电路中具有优选的高频电特性。